SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The direct TR submission can be atomic or nonatomic. There is one atomic register set that allows for a TR to be submitted with a single burst write. There are also three nonatomic register sets for nonatomic direct TR submission. Each of these three sets allows direct TR submission without requiring submission in a single burst.
The direct atomic TR submission is handled through DRU register writes to the DRU_ATOMIC_SUBMIT_CURR_TR_WORD0_1_j to DRU_ATOMIC_SUBMIT_CURR_TR_WORD14_15_j registers which require write in a single 64-byte burst. Any write other than this size returns an address error. All burst values are checked if they are legal values and space in the channel FIFO is checked too. Then the TR is pushed into the FIFO and the write status is returned with success. If any of the legal TR format checks or FIFO space check fails or if the channel is not owned and enabled the result is an address error returned.
The direct nonatomic TR submission is handled through DRU register writes to the DRU_SUBMIT_WORD0_1_j_k to DRU_SUBMIT_WORD14_15_j_k registers which are intended to be used for cores not being able to perform a large burst write in a single cycle. There is a single set for each core regardless of the channel number. A write to the DRU_SUBMIT_WORD0_1_j_k register triggers the TR.
The following should be taken into account: