SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
This section lists all formulas to calculate synchronous NOR timing parameters. This is the case when GPMC_CONFIG1_i[11-10] DEVICETYPE = 0x0 and when READTYPE or WRITETYPE are set to synchronous mode. Table 12-275 describes the synchronous NOR formulas.
Configuration Parameter | Unit | Description |
---|---|---|
A | ns | Pulse duration – nCS low |
B | ns | Delay time – address bus valid to CLK first edge |
Delay time – nBE0 / nBE1 valid to CLK first edge | ||
C | ns | Pulse duration – nBE0 / nBE1 low |
D | ns | Delay time – CLK rising edge to nBE0 / nBE1 invalid |
Delay time – CLK rising edge to nADV/ALE invalid | ||
E | ns | Delay time – CLK rising edge to nCS invalid |
Delay time – CLK rising edge to nOE/nRE invalid | ||
F | ns | Delay time – CLK rising edge to nCS transition |
G | ns | Delay time – CLK rising edge to nADV/ALE transition |
H | ns | Delay time – CLK rising edge to nOE/nRE transition |
I | ns | Delay time – CLK rising edge to nWE transition |
J | ns | Delay time – CLK rising edge to A[16-1/]D[15-0] data bus transition |
Delay time – CLK rising edge to nBE0 / nBE1 transition | ||
K | ns | Pulse duration – nADV/ALE low |
L | ns | Delay time – WAIT invalid to first data latching CLK edge |
The configuration parameters are calculated through the following formulas. For more information, see the device-specific Datasheet.
Figure 12-163 shows a simplified example of a synchronous NOR single read where formulas are associated with signal waves.