SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Separate (INTA_ENABLE_SET_j and INTA_ENABLE_CLEAR_j) registers are provided to allow individual enable bits to be enabled or disabled without the need for a read-modify-write operation. When the INTA_ENABLE_SET_j register is written, all bits within written bytes which are 1 will cause corresponding bits in the internal enable register to be set. When the INTA_ENABLE_CLEAR_j register is written, all bits within written bytes which are 1 will cause corresponding bits in the internal enable register to be cleared.