SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The VISS node scheduler comprises 3 consumer sockets and 6 producer sockets. On consumer side, it is only connected to the DMA producer scheduler. On producer socket, it is only connected to the DMA consumer scheduler.
The consumer sockets are mapped to:
The producer sockets are mapped to the following output buffers:
Pipeline #n (n = 0, …, 6 configurable) is mapped to this scheduler. When a scheduler is enabled, the DMA producer scheduler triggers UTC data loading from DDR memory into the SL2 memory. Once data is available inside the SL2 memory, the VISS scheduler starts a VISS thread. Prior to starting a VISS thread, the buffer availability to write output data is checked. These consumer and producer sockets can optionally be disabled depending on the usecase.
To enable streaming data support, this scheduler node supports a streaming feature. That is, the scheduler does not go into idle state after the end of the pipe, rather it transitions to initialization state to save host intervention between frame in OTF (on-the-fly) mode.