SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
This section describes the DPHY_RX application fields from an environment point of view (external connections).
Table 12-473 describes the external signals of the DPHY_RX.
Device Level Signal | I/O | Description |
---|---|---|
CSI0_RXN0 | I | Lane 0 Receive Differential Data (Negative) |
CSI0_RXP0 | I | Lane 0 Receive Differential Data (Positive) |
CSI0_RXN1 | I | Lane 1 Receive Differential Data (Negative) |
CSI0_RXP1 | I | Lane 1 Receive Differential Data (Positive) |
CSI0_RXN2 | I | Lane 2 Receive Differential Data (Negative) |
CSI0_RXP2 | I | Lane 2 Receive Differential Data (Positive) |
CSI0_RXN3 | I | Lane 3 Receive Differential Data (Negative) |
CSI0_RXP3 | I | Lane 3 Receive Differential Data (Positive) |
CSI0_RXCLKN | I | Lane 3 Receive Differential Clock (Negative) |
CSI0_RXCLKP | I | Lane 3 Receive Differential Clock (Positive) |
CSI0_RXRCALIB | A | Pin for external calibration resistor. An external resistor must be connected between this pin and package ground. Refer to the device-specific Datasheet for a recommended resistor value. |
CSI1_RXN0 | I | Lane 0 Receive Differential Data (Negative) |
CSI1_RXP0 | I | Lane 0 Receive Differential Data (Positive) |
CSI1_RXN1 | I | Lane 1 Receive Differential Data (Negative) |
CSI1_RXP1 | I | Lane 1 Receive Differential Data (Positive) |
CSI1_RXN2 | I | Lane 2 Receive Differential Data (Negative) |
CSI1_RXP2 | I | Lane 2 Receive Differential Data (Positive) |
CSI1_RXN3 | I | Lane 3 Receive Differential Data (Negative) |
CSI1_RXP3 | I | Lane 3 Receive Differential Data (Positive) |
CSI1_RXCLKN | I | Lane 3 Receive Differential Clock (Negative) |
CSI1_RXCLKP | I | Lane 3 Receive Differential Clock (Positive) |
CSI1_RXRCALIB | A | Pin for external calibration resistor. An external resistor must be connected between this pin and package ground. Refer to the device-specific Datasheet for a recommended resistor value. |