SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The PCIe Core module supports dual mode of operation - it can be configured as an End Point (EP) and also as a Root Port (RP). The operational mode is selected with the CTRLMMR_PCIE1_CTRL[7] MODE_SEL register bit within the device Control Module (CTRL_MMR0). It is expected that the MODE_SEL bit is programmed during initial power up based on settings in the SoC boot configuration or a non-volatile storage such as eFuse or Flash memory.
It is not expected that the MODE_SEL setting would have to change during a full power cycle of the device. It is more likely that the operational mode of a SoC will stay as EP or RP for a particular end product’s life cycle. It is not expected to switch back and forth during operation without a reset cycle.
The PCIe core module supports four virtual channels (VC) and four transfer classes (TC). The VCs can be used to implement Quality-of-Service (QoS) mechanism by enabling priority or round-robin arbitration. Typically, the highest numbered enabled VC is assigned the highest priority.
The PCIe core module is configured to support Single Root I/O virtualization (SR-IOV). It supports 6 Physical Functions (PF) and 16 Virtual Functions (VF).
There is one AXI master port and one AXI slave port in the PCIe core. All ingress data traffic regardless of the VC assigned will be delivered on the AXI master port. Similarly, all egress data that is presented on AXI slave port of the PCIe core will be assigned VCs through the outbound address translation registers.