The debug capabilities that are deployed within
the Compute Cluster are mostly deployed at lower levels of hierarchy, that is within
the processor subsystems and the MSMC. Some of these features require special
handling at the Compute Cluster level. This includes:
- Debug ROM table
- Facilitates tooling software’s identification of
debug resources embedded within the Compute Cluster and underlying
processor subsystems
- Debug configuration
- Supported via CBA VBUSP interface
- Provides a dedicated configuration path for debug components within the Compute Cluster
- Remote and embedded debuggers, debug libraries, and application code use this interface to configure and use debug features embedded at different levels of hierarchy within the Compute Cluster
- Compute Cluster address map is 64MB
- Cross triggering
- Supported via Arm Coresight Channel Interface
(CI)
- Provides support for management of triggering resources within the Compute Cluster and across the SoC
- Arm CoreSight Cross Trigger Matrix (CTM) supports
the management of multiple CoreSight Channel
Interface (CI) interfaces
- Trace data path
- Supported via AMBA ATB v1.1 interface
- Provides support for merging of one or more trace streams into a common trace data path through the use of a CoreSight ATB Trace Funnel
- ATB interface includes some key trace specific functions including in-band flushing and synchronization requests
- Debug time distribution
- Supported via Arm Coresight Wide Timestamp
Interface (WTI)
- Facilitates the distribution of the 48-bit global debug time to the various trace sources that exist inside the Compute Cluster hierarchy