SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Through the MSMC_WBINV_CTRL register MSMC provides control for software to trigger a coherent invalidation of MSMC external or internal SRAM snoop filters. If the MSMC_WBINV_CTRL[0] EMIF_SF_WBINV bit is set to 1h, then MSMC will invalidate the external snoop filter, writing back any dirty data to EMIF. If the MSMC_WBINV_CTRL[4] SRAM_SF_WBINV bit is set to 1h, then MSMC will invalidate the internal SRAM snoop filter and write back any dirty data into its own SRAM. If both fields are written to simultaneously, then MSMC will invalidate the external snoop filter before invalidating the internal SRAM snoop filter immediatly afterwards. As part of the write back invalidation procedure, MSMC will request all coherent masters to invalidate any lines that MSMC is tracking.
When the write back invalidation of the external or internal SRAM SF is triggered the MSMC_WBINV_CTRL[8] WBINV_ACTIVE bit is set to 1h until all invalidations are complete at which time the bit is reset to 0h. Due to shared hardware between snoop filter invalidation and cache resizing for looping though all of the snoop filter entries, any write to EMIF_SF_WBINV, SRAM_SF_WBINV, or the MSMC_CACHE_CTRL[3-0] CACHE_SIZE field will be ignored if the WBINV_ACTIVE bit is 1h. Similarly, writes to EMIF_SF_WBINV and SRAM_SF_WBINV are ignored if a cache resize is in progress.
MSMC will maintain coherency for any transactions that arrive during a write back invalidation procedure, although the snoop filter state for any addresses they access is not guaranteed to be invalid until the operation is complete. The snoop filter state for any address accessed during the invalidation of the associated snoop filter depends on whether or not the access occurs before or after MSMC has performed its write back invalidation on that particular snoop filter entry.