SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 6-44 give hints on handling configuration error interrupts.
Memory | Error Generation Window | HWA-level Register Status Clearing Mechanism |
---|---|---|
RAWFE | ||
PWL1_LUT, PWL2_LUT, PWL3_LUT | Config read access during active line OR write access during active frame. | Write ‘1’ to corresponding bit in RAWFE_INT_STAT register. |
WDR_LUT | ||
H3A_LUT | ||
H3A_ACCM | Config read/write access during active frame at H3A boundary. | |
H3A_LINE | ||
DPC_LUT | Config read/write access during active frame. | |
DPC_LINE | Config read access during active line OR write access during active frame. | |
LSC Table | Config read/write access during active frame. Active frame in lsc case is VS at pwl to VE at lsc input delayed by 1 cycle. | |
NSF4V | ||
NSF4V_LINE | Config read/write access when datapath is accessing the corresponding memory on the same cycle. | No register status in NSF4V. |
GLBCE | ||
GLBCE non-shadowed registers | Config write access during active frame. Active frame window is from VS_IN to Filter done. | Write ‘1’ to GLBCE_INT_STAT[0] MMR_CFG_ERR register bit. |
GLBCE_STAT | Config read/write access during active frame. Active frame window is from VS_IN to Filter done. | Write ‘1’ into GLBCE_INT_STAT[1] STATMEM_CFG_ERR register bit. |
GLBCE_LINE | Not mapped to config. | N/A |
CFA | ||
CFA FIR Filter registers | Config write access during active frame. | Write ‘1’ to CFA_INT_STATUS[2] CFA_MMR_ERR register bit. |
CFA_LUT | Config read/write access during active frame. | Write ‘1’ into CFA_INT_STATUS[0] LUT_CFG_ERR register bit. |
CFA_LINE | Config read/write access during active frame. | Write ‘1’ to CFA_INT_STATUS[1] CFA_PIX_ERR register bit. |
FCC | ||
LUT_CONTRAST | Config access (read/write) occurs during active line when the LUT is enabled. | Write ‘1’ to corresponding bit in FCC_FLEXCC_INT_STATUS register. |
HISTOGRAM | Config access has occurred to the first location but not to the last location till the start of next frame implying that full histogram was not read. | |
LUT_COLOR | Config access (read/write) occurs during active line when the LUT is enabled. | |
CC_LINE | No error generation logic. | N/A |
EE | ||
EE_LINE | Config accesses during active frame. | Write ‘1’ to EE_INT_STATUS[1] EE_PIX_ERR register bit. |
LUT | Config accesses during active frame. | Write ‘1’ to EE_INT_STATUS[0] EELUT_CFG_ERR register bit. |