SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
MSC does not support shadow registers for its configuration registers. All changes must be done prior to the HTS.INIT request for a frame processing.
Input and output channels are individually enabled. It is expected that at least one input and output channels are enabled for each HTS thread enabled.
The MSC does not check for proper programming of all configuration parameters. It is strictly software responsibility to ensure programming of MSC (Core and LSE) registers do not cause conflict with each other.