SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Figure 12-209 and Table 12-294 show a task issuance sequence.
Step | Description |
---|---|
1 | Find an empty transfer request slot by reading the MMCSD0_CQ_TASK_DOOR_BELL register. An empty transfer request slot has its respective bit cleared to '0' in the MMCSD0_CQ_TASK_DOOR_BELL register. |
2 | Build a Task Descriptor at the 1st entry of the empty slot. Task Descriptor field values:
|
3 | Build a Transfer Descriptor at the 2nd entry of the empty slot. Transfer Descriptor field values:
|
4 | If more than one transfer is requested, repeat step 1-3 for all needed transfers. |
5 | Set MMCSD0_CQ_TASK_DOOR_BELL register to indicate to the CQE that one or more transfer requests are ready to be sent to the attached device. Host software shall only write a '1' to the bit position that corresponds to new tasks; all other bit positions within MMCSD0_CQ_TASK_DOOR_BELL register should be written with a '0', which indicates no change to their current values. |