SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The A72 cluster is provided by Arm and configured by TI. Table 6-2 summarizes the configuration of the A72 cluster for this device.
Parameter | Value |
---|---|
Core type | A72(1) |
Number of cores | 2 |
Bus width | 512 |
L1 instruction cache size | 48K |
L1 data cache size | 32K |
L2 cache size | 2MB |
ECC protection for L2 cache | Included |
ECC/parity protection for CPU cache | Included |
Advanced SIMD and Floating Point Extension | Included |
Cryptography extension | Included |
L2 FEQ size | 28 |