SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Step | Description |
---|---|
1. | Ensure that the FIFO RAM auto-initialization is complete by reading the MCU_FSS0_HPB0_SS_RAM_STAT_REG[0] INIT_DONE bit . |
2. | Lock MDLL: |
- To ensure that the MDLL in the HyperBus is locked, the reset to the HyperBus module should be de-asserted only after all the clock inputs are stable at the desired operating frequency (see MCU_FSS0_HPB0 Clocks and Resets). The MDLL can lose the lock if the frequencies of the clock inputs to the HyperBus module are changed during operation. | |
- To ensure that the MDLL is stabilized, the following sequence is required. Boot code should attempt to read 64 bytes of Flash data, for 16 iterations, and if the data is the same in 4 successive iterations, the DLL can be considered to be stabilized and the software proceed with normal Flash access . | |
- The MCU_FSS0_HPB0_SS_DLL_STAT_REG[0] MDLL_LOCK and MCU_FSS0_HPB0_SS_DLL_STAT_REG[1] SDL_LOCK bits can be used to determine if the master delay line and slave delay line have locked, respectively . | |
3. | Initialize Memory Configuration register (MCU_FSS0_HPB0_MC_MCR_y): |
- MCU_FSS0_HPB0_MC_MCR_y[31] MAXEN bit and MCU_FSS0_HPB0_MC_MCR_y[26-18] MAXLEN bit field based on burst transaction length to memory. | |
- MCU_FSS0_HPB0_MC_MCR_y[17] TCMO = 1h, to enable HBMC to merge multiple accesses with sequential addresses into a single memory access. This will improve memory throughput. | |
- MCU_FSS0_HPB0_MC_MCR_y[16] ACS = 0h, to set 'No asymmetry cache system support'. | |
- MCU_FSS0_HPB0_MC_MCR_y[5] CRT = 0h, to set 'Memory space' instead 'CR space'. | |
- MCU_FSS0_HPB0_MC_MCR_y[4] DEVTYPE = 0h, to set 'HyperFlash' instead 'HyperRAM'. | |
- MCU_FSS0_HPB0_MC_MCR_y[1-0] WRAPSIZE = 00h, since the HBMC does not support wrap bursts. | |
4. | Initialize Memory Timing register (MCU_FSS0_HPB0_MC_MTR_y) based on timing of the memory device being used. |
5. | Initialize Memory Base Address register (MCU_FSS0_HPB0_MC_MBAR_y): |
- MCU_FSS0_HPB0_MC_MBAR_y[31-24] A_MSB = 8 MSB bits of memory address space. This will define the start of the 16 MB address region in the system memory where the HyperFlash can be accesed. The HBMC will initiate HyperFlash access to any memory mapped access in this range. | |
6. | Check the MCU_FSS0_HPB0_MC_CSR[10] RRSTOERR bit in Controller Status register to ensure that the HyperFlash is out of reset. |
7. | Normal HyperFlash access can be performed after this. |
8. | The HyperFlash device registers and CFI (Common Flash Interface) region can be accessed by read/write transactions to the offset from the base address as specified in the device command summary table. |
9. | The HyperFlash memory data array can be read as memory mapped access. |
10. | The HyperFlash write sequence needs to be followed to update contents of the memory array. |