SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
In this SoC, the DEBUGSS resides in the VD_CORE voltage domain and is powered down in many power modes. In order to be able to reliably connect the debug tooling (via JTAG port), there is a requirement to support debug connection only when VD_WAKE is powered on. To accomplish this, an ICEMelter module is instantiated in VD_WAKE, and the EMU0/1, TCK and nTRST JTAG signals are mapped to I/O pins in VD_WAKE. The ICEMelter monitors these I/O signals and upon detecting an active debug connection, it signals the to force a wakeup of VD_CORE and associated DEBUGSS power domain (PD_DEBUG). DEBUGSS and associated logic remain powered, clocked and out of reset for as long as ICEMelter is detecting an active debug connection.
In addition, the boot modes selected by EMU0/1 at device POR are detected and held until the DEBUGSS is powered. These modes can be used to put the device in wait-in-reset (WIR) mode, where all subdomains other than the are held in reset awaiting a debug connection. The supports an operating sequence that detects WIR assertion during the boot process. For a GP device, the ROM spins near the beginning of the boot sequence, allowing the debug tools to connect before the majority of the ROM code executes. Once connected, the debug tool can be used to move the PC past the spin and the ROM code can be executed under debug control.
As referenced above, the ICEMelter module interacts with and DEBUGSS and can manage debug behavior of the device right from POR by sampling the EMU0/1 pin interface. The details are defined in Table 13-6.
Boot Mode | EMU1 | EMU0 | Actions |
---|---|---|---|
Normal | 1 | 1 | Device boots nomally. Debug can connect at any time, but the context will be post boot. |
Wait‐in‐Reset (WIR) | 1 | 0 | 1. ICEMelter asserts WIR active signal to and DEBUGSS. |
2. samples the WIR active input at boot to determine behavior for boot. | |||
3. DEBUGSS asserts WIR request for all subdomains managed via Power‐AP. | |||
4. Device remains essentially quiescent until debug can connect and release WIR for debug of boot sequences. | |||
Reserved | 0 | 1 | Behavior is undefined. |
Reserved | 0 | 0 | Behavior is undefined. |