SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Some of the GMPC features described in this section may not be supported on this family of devices. For more information, see GPMC Not Supported Features.
This section describes the bit field to configure to set the GPMC in various memory modes. Table 12-271 and Table 12-272 provide check lists for mode parameters and access type parameters, respectively.
Register | Bit | Name | Asynchronous | Synchronous | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Single Read Access | Single Write Access | Multiple Read (Page) Access | Multiple Write (Page) Access | Single Read Access | Single Write Access | Multiple Read (Burst) Access | Multiple Write (Burst) Access | |||
GPMC_CONFIG1_i | 30 | READMULTIPLE | 0x0 | Don't care | 0x1 (1) | Not Supported | 0x0 | Don't care | 0x1 | Don't care |
GPMC_CONFIG1_i | 29 | READTYPE | 0x0 | Don't care | 0x0 (1) | Not Supported | 0x1 | Don't care | 0x1 | Don't care |
GPMC_CONFIG1_i | 28 | WRITEMULTIPLE | Don't care | 0x0 | - (1) | Not Supported | Don't care | 0x0 | Don't care | 0x1 |
GPMC_CONFIG1_i | 27 | WRITETYPE | Don't care | 0x0 | - (1) | Not Supported | Don't care | 0x1 | Don't care | 0x1 |
Register | Bit | Name | Access Type | ||
---|---|---|---|---|---|
non-multiplexed | Address/ Data-Multiplexed | AAD-Multiplexed | |||
GPMC_CONFIG1_i | 9-8 | MUXADDDATA | 0x0 | 0x2 | 0x1 |