SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The goal of the basic high-level programming model is to introduce a top-down approach to users that need to configure the GPMC module.
Figure 12-160 and Table 12-257 through Table 12-258 show a programming model top-level diagram for the GPMC, and a description of each step. Each block of the diagram is described in one of the following sections through a set of registers to configure.
Step | Description |
---|---|
NOR Memory Type | See Table 12-259. |
NOR Chip-Select Configuration | See Table 12-260. |
NOR Timings Configuration | See Table 12-261. |
WAIT Pin Configuration | See Table 12-269. |
Enable Chip-Select | See Table 12-270. |
Step | Description |
---|---|
NAND Memory Type | See Table 12-264. |
NAND Chip-Select Configuration | See Table 12-265. |
Write Operations (Asynchronous) | See Table 12-266. |
Read Operations (Asynchronous) | See Table 12-266. |
ECC Engine | See Table 12-267. |
Prefetch and Write-Posting Engine | See Table 12-268. |
WAIT Pin Configuration | See Table 12-269. |
Enable Chip-Select | See Table 12-270. |