SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The DDR controller contains an arbitration block that has software programmable interface for low power control. Placement of and removal from the various memory low power modes is controlled through programming of registers in the DDR controller. The user can also monitor the status of the memory devices through a programmable register. This interface supports a lock option allowing software to execute additional commands through this interface without worrying about state changes through other interfaces.