SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 5-48 lists the clock synthesis parameters for PLLTS16FFCLAFRAC2 and PLLTS16FFCLAFRACF types.
Parameter Name | Register |
---|---|
FBDIV | <PLL_name>_FREQ_CTRL0[11-0] FB_DIV_INT (For example, MCU_PLL0 - MCU_PLL0_FREQ_CTRL0[11-0] FB_DIV_INT) |
FRAC | <PLL_name>_FREQ_CTRL1[23-0] FB_DIV_FRAC (For example, MCU_PLL0 - MCU_PLL0_FREQ_CTRL1[23-0] FB_DIV_FRAC) |
POSTDIV2 | <PLL_name>_DIV_CTRL[26-24] POST_DIV2 (For example, MCU_PLL0 - MCU_PLL0_DIV_CTRL[26-24] POST_DIV2) |
POSTDIV1 | <PLL_name>_DIV_CTRL[18-16] POST_DIV1 (For example, MCU_PLL0 - MCU_PLL0_DIV_CTRL[18-16] POST_DIV1) |
REFDIV | <PLL_name>_DIV_CTRL[5-0] REF_DIV (For example, MCU_PLL0 - MCU_PLL0_DIV_CTRL[5-0] REF_DIV) |
Table 5-49 lists the clock synthesis parameters for PLLTS16FFCLVDESKEWC type.
For PLLTS16FFCLAFRAC2 and PLLTS16FFCLAFRACF types - POSTDIV1 and POSTDIV2 values are from 1 to 7. To ensure correct operation, POSTDIV1 must always be programmed to a value equal to or greater that POSTDIV2.
Parameter Name | Register |
---|---|
FBDIV | <PLL_name>_DIV_CTRL[13-12] FB_DIV (For example, PLL24 - PLL24_PLL_DIV_CTRL[13-12] FB_DIV) |
POSTDIV | <PLL_name>_DIV_CTRL[10-8] POST_DIV (For example, PLL24 - PLL24_PLL_DIV_CTRL[10-8] POST_DIV) |
REFDIV | <PLL_name>_DIV_CTRL[1-0] REF_DIV (For example, PLL24 - PLL24_PLL_DIV_CTRL[1-0] REF_DIV) |
For PLLTS16FFCLVDESKEWC type: