SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
This section describes the interfaces handled by the Display Subsystem.
Table 12-401 describes the DSS DPI parallel interface I/O signals.
Module Pin | I/O(1) | Description |
---|---|---|
DSS_DPI0_DATA[23:0] | O | Pixel data output. RGB data for MIPI DPI 2.0 interface. YUV data for BT.656/BT.1120 interfaces. |
DSS_DPI0_VSYNC | O | Vertical synchronization. The frame synchronization pulse (vsync) toggles after all the lines in a frame are transmitted and a programmable number of line clock cycles has elapsed at the beginning and the end of each frame. |
DSS_DPI0_HSYNC | O | Horizontal synchronization. The line synchronization pulse (hsync) toggles after all pixels in a line are transmitted and a programmable number of pixel clock wait-states has elapsed at the beginning and the end of each line. |
DSS_DPI0_PCLK | O | Pixel clock output. |
DSS_DPI0_DE | O | Pixel data output-enable signal to indicate when data must be latched using the pixel clock. |
DSS_DPI0_EXTPCLKIN | I | Pixel clock input from external source. |
DSS_DPI1_DATA[15:0] | O | Pixel data output. RGB data for MIPI DPI 2.0 interface. YUV data for BT.656/BT.1120 interfaces. |
DSS_DPI1_VSYNC | O | Vertical synchronization. Vertical synchronization. The frame synchronization pulse (vsync) toggles after all the lines in a frame are transmitted and a programmable number of line clock cycles has elapsed at the beginning and the end of each frame. |
DSS_DPI1_HSYNC | O | Horizontal synchronization. Horizontal synchronization. The line synchronization pulse (hsync) toggles after all pixels in a line are transmitted and a programmable number of pixel clock wait-states has elapsed at the beginning and the end of each line. |
DSS_DPI1_PCLK | O | Pixel clock output. |
DSS_DPI1_DE | O | Pixel data output-enable signal to indicate when data must be latched using the pixel clock. |
DSS_DPI1_EXTPCLKIN | I | Pixel clock input from external source. |
Table 12-402 describes the DSI I/O signals.
Device Level Signal | I/O(1) | Description |
---|---|---|
DSI_TXN0 | I/O | External differential I/O Lane 0 |
DSI_TXP0 | I/O | |
DSI_TXN1 | O | External differential output Lane 1 |
DSI_TXP1 | O | |
DSI_TXN2 | O | External differential output Lane 2 |
DSI_TXP2 | O | |
DSI_TXN3 | O | External differential output Lane 3 |
DSI_TXP3 | O | |
DSI_TXCLKN | O | External differential clock Lane |
DSI_TXCLKP | O | |
DSI_TXRCALIB | A | Pin for external calibration resistor |
DSI_ATB_0_H | I/O | Analog test bus |
DSI_ATB_1_H | I/O |
Table 12-403 describes the EDP I/O signals.
Device Level Signal | I/O(1) | Description |
---|---|---|
DP0_TX0_N | O | External differential output Lane 0 |
DP0_TX0_P | O | |
DP0_TX1_N | O | External differential output Lane 1 |
DP0_TX1_P | O | |
DP0_TX2_N | O | External differential output Lane 2 |
DP0_TX2_P | O | |
DP0_TX3_N | O | External differential output Lane 3 |
DP0_TX3_P | O | |
DP0_AUXN | I/O | Auxiliary channel differential transceiver |
DP0_AUXP | I/O | |
DP0_AUX_ATB_0 | I/O | Analog test bus |
DP0_AUX_ATB_1 | I/O | |
EDP | ||
DP0_HPD | I | Hot plug detect input |