SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The DDR controller has a BIST engine that supports MOVI3N and limited MOVI algorithms, a self-refresh retention test, an idle retention test and a memory initialization test for detecting the following faults:
The DDR controller also supports BIST on ECC lanes for out-of-band ECC configuration. The following are the BIST related registers: