The C71SS (C71x CorePac) supports the following
key features:
- Hierarchical cache memory system
- Level 1 (L1):
- L1 program memory controller (PMC) with associated L1 program memory (L1P)
- L1 data memory controller (DMC) with associated L1 data memory (L1D), either L1 data cache or L1 scratch memory
- Level 2 (L2):
- L2 unified memory controller (UMC) with associated L2 memory, either L2 cache or L2 scratch memory
- Streaming engine (SE)
- CorePac memory management unit (CMMU), fully compliant with Armv8-A memory architecture
- Power/clock/reset management unit
- ECC/parity support
- ECC protection of L2 memory and L1D memory
- Parity protection of L1P memory
- PBIST and LBIST support
- Cluster Level Event Controller (CLEC) CPU interface
- C71x debug subsystem
- Extended configuration register (ECR) interface for register access (instead of MMR)