SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
After a reset or a previous teardown operation but before queuing packets to a channel the host must initialize the channel’s Tx Port DMA State. The host initializes the channel Tx Port DMA State by writing to the Tx Channel Configuration Register A. The Host may choose to write the enable bit in the Tx Channel Configuration Register A at the same time or after it has written all of the channel parameters but note that every write to the Tx Channel Configuration Registers will overwrite the channel state for all bytes that are enabled for the write transaction.
It should be noted that very little configuration information is required for a UDMA Tx channel compared to previous versions of UDMA. This is because UDMA has transitioned to a full modeless model for channel operation where each packet descriptor specifies the descriptor type, packet type, and the packet return parameters. Packet queues in UDMA may include combinations of host and monolithic descriptors in any order.
After a Transmit channel has been set up, packets can be added to the Queues for the channel to begin the transmit operation. The following sections describe how the transmit operations are performed for the various descriptor types.