SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The normal operation of the controller allows the firmware to build a message and then issue the transaction to the I3C controller. The command queue is provided in order to allow the host to load a request for multiple messages. Single message consists of two 32-bit words (Command Word0 and Command Word1). In order to issue the transaction the following procedure should be followed:
If controller is enabled (I3C_CTRL[31] DEV_EN bit is set to 0x01), writing Command Word0 triggers the execution of the command, resulting in start condition on the I3C bus.