SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The block diagram of PCIe subsystem is shown in Figure 12-118. The subsystem comprises of these major components – the PCIe Core with AXI interfaces, bridges to connect to the system CBASS0 interconnect master and slave interfaces, bridges to connect the system CBASS0 configuration interfaces, additional logic to implement the Precision Time Measurement (PTM), user configuration and interrupt, and RAMs to support the controller FIFOs.
Figure 12-118 also shows some example data flows in the PCIe subsystem, such as: