SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
There is a reprogramming module that runs in lock step with the FSM, always one state ahead – the FSM exports its next_state for use by the reprogramming RAM.
This RAM keeps track of the setup values for the timers as programmed by the TIMERMGR_SETUP_j_k memory mapped locations. There is a SET flag for each timer outside of the RAM – if this SET flag is true for the next_state timer, the VBUS ready signals are deasserted; if there is a pending timer setup, there cannot be a read or write to the memory, as this would interrupt the Timer FSM state machine and, with enough accesses, potentially cause the system to exceed the 10-µs window for timer accuracy.