SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The DDR PHY provides functionality to interface the DDR controller to SDRAM devices. The PHY has a slice based and DQS-delay architecture. It contains data, address, address/control and clock slices and uses programmable clock delay lines to align write data, read data capture, and DQS gating from the I/O pads across the DFI interface to the DDR controller.