SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Normal debug actions should not corrupt the correctness of the application and should keep the intrusion to the application to a minimum. This requires that all peripherals that are sensitive to debug events should be debug aware. Specifically:
The SoC supports a suspend mechanism which provides a means to stop a closely-coupled hardware process running on a device peripheral when the host processor enters debug state. The suspend mechanism is important for debug to ensure that peripherals operate in a lock-step manner with a host processor. To facilitate the operation of such peripherals, each of the following processors in the SoC outputs a group of signals indicating their execution state:
Accordingly, an entry is provided for each peripheral that needs to take into account the suspend signals from these processors. Typically, one or two bits (FREE and/or SOFT) are implemented in the peripheral register dedicated to debug suspend control. The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral function is required or if the peripheral suspend should occur only after a particular completion point is reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the debug suspend functionality.
The SoC debug framework provides a configurable debug suspend to peripheral mapping that allows shared peripherals to be configured to honor the halt signal from any debug target in the system. This is accomplished via a debug suspend router (DBGSUSP_RTR) which represents an array of muxes and a set of associated control registers. CPU suspend outputs are mapped to DBGSUSP_RTR inputs and peripheral suspend inputs are mapped to DBGSUSP_RTR outputs.
summarize the suspend sources (device CPUs) and suspend sinks (device peripherals) mapping, respectively.