SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The LDC does not need thread management on its input buffer. The LDC uses its own DMA engine to fetch required input data. The LDC needs DMA to write out its output data and needs HTS interface. Refer to chapter Data Routing Unit (DRU), about DMA configuration for data store. Maximum 13 DMA channels need to be set up for writing out output data.