SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Figure 6-18 captures top level overview of FCP. LUT in front on CFA can map 16-bit data to 12-bit when CFA is operating in 12-bit mode. It can also be used to 16b to 16b remap when CFA is operating in 16-bit mode. EE data path is clock gated when EE module is not used. EE has bypass condition (YEE = 0) where data flows thorough it unchanged with the same latency as the enable condition.
In the CC module, Y12 to Y8 and U12 to UV8 LUTs should be enabled or disabled together (i.e CFG_2.C8LutEn = CFG_2.C8LutEn).
Program EE_CFG_1.Yuv8_cl_align = 1 while generating interleaved 422 8-bit and EE_CFG_1.Yuv12_cl_align = 1 while generating interleaved 422 12-bit output. This function is available even when EE path is not used.