SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
A Power Glitch Detect (PGD) circuit is used to detect short duration “glitches” on the core and MPU power supplies. The PGD provides a low output when no glitch is detected and a high output when a glitch is detected.
Figure 5-6 shows the PGD block diagram.
Table 5-21 summarize the PGD integration.
Module Instance | Monitored Voltage | PGD Control/Status Registers |
---|---|---|
IPGD_VDD_MCU_CORE | VDD_MCU | CTRL_MMR_VDD_MCU_GLDTC_CTRL |
CTRL_MMR_VDD_MCU_GLDTC_STAT | ||
IPGD_VDD_MCU_MEM | VDDR_MCU (SRAM) | CTRL_MMR_VDDR_MCU_GLDTC_CTRL |
CTRL_MMR_VDDR_MCU_GLDTC_STAT | ||
IPGD_VDD_CPU_CORE | VDD_CPU | CTRL_MMR_VDD_CPU_GLDTC_CTRL |
CTRL_MMR_VDD_CPU_GLDTC_STAT | ||
IPGD_VDD_MAIN_CORE | VDD_CORE | CTRL_MMR_VDD_CORE_GLDTC_CTRL |
CTRL_MMR_VDD_CORE_GLDTC_STAT | ||
IPGD_VDD_CPU_MEM | VDDR_CPU (SRAM) | CTRL_MMR_VDDR_CPU_GLDTC_CTRL |
CTRL_MMR_VDDR_CPU_GLDTC_STAT | ||
IPGD_VDD_MAIN_MEM | VDDR_CORE (SRAM) | CTRL_MMR_VDDR_CORE_GLDTC_CTRL |
CTRL_MMR_VDDR_CORE_GLDTC_STAT | ||
IPGD_VDD_CPU1_CORE | VDD_CORE | CTRL_MMR_VDD_CPU1_GLDTC_CTRL |
CTRL_MMR_VDD_CPU1_GLDTC_STAT |
A flag status bit in corresponding STAT register is cleared by clearing the [30] RSTB bit in the corresponding CTRL register, see for STAT and CTRL registers for a certain PGD module.