Before initialization, the user should program the
FSP-related mode registers (MR1, MR2, MR3, MR11, MR12, MR13, MR14 and MR22) with the
relevant values, and the DDRSS_CTL_21[28-24] DFIBUS_FREQ_F2, DDRSS_CTL_21[20-16]
DFIBUS_FREQ_F1 and DDRSS_CTL_21[12-8] DFIBUS_FREQ_F0 fields with the frequency set
to use. These mode registers are programmed through the following fields:
- DDRSS_CTL_175[7-0]
MR1_DATA_F0_0
- DDRSS_CTL_175[23-16]
MR1_DATA_F1_0
- DDRSS_CTL_176[7-0]
MR1_DATA_F2_0
- DDRSS_CTL_182[23-16]
MR1_DATA_F0_1
- DDRSS_CTL_183[7-0]
MR1_DATA_F1_1
- DDRSS_CTL_183[23-16]
MR1_DATA_F2_1
- DDRSS_CTL_175[15-8]
MR2_DATA_F0_0
- DDRSS_CTL_175[31-24]
MR2_DATA_F1_0
- DDRSS_CTL_176[15-8]
MR2_DATA_F2_0
- DDRSS_CTL_182[31-24]
MR2_DATA_F0_1
- DDRSS_CTL_183[15-8]
MR2_DATA_F1_1
- DDRSS_CTL_183[31-24]
MR2_DATA_F2_1
- DDRSS_CTL_176[31-24]
MR3_DATA_F0_0
- DDRSS_CTL_177[7-0]
MR3_DATA_F1_0
- DDRSS_CTL_177[15-8]
MR3_DATA_F2_0
- DDRSS_CTL_184[15-8]
MR3_DATA_F0_1
- DDRSS_CTL_184[23-16]
MR3_DATA_F1_1
- DDRSS_CTL_184[31-24]
MR3_DATA_F2_1
- DDRSS_CTL_178[23-16]
MR11_DATA_F0_0
- DDRSS_CTL_178[31-24]
MR11_DATA_F1_0
- DDRSS_CTL_179[7-0]
MR11_DATA_F2_0
- DDRSS_CTL_186[7-0]
MR11_DATA_F0_1
- DDRSS_CTL_186[15-8]
MR11_DATA_F1_1
- DDRSS_CTL_186[23-16]
MR11_DATA_F2_1
- DDRSS_CTL_179[15-8]
MR12_DATA_F0_0
- DDRSS_CTL_179[23-16]
MR12_DATA_F1_0
- DDRSS_CTL_179[31-24]
MR12_DATA_F2_0
- DDRSS_CTL_186[31-24]
MR12_DATA_F0_1
- DDRSS_CTL_187[7-0]
MR12_DATA_F1_1
- DDRSS_CTL_187[15-8]
MR12_DATA_F2_1
- DDRSS_CTL_180[7-0]
MR13_DATA_0
- DDRSS_CTL_180[15-8]
MR14_DATA_F0_0
- DDRSS_CTL_180[23-16]
MR14_DATA_F1_0
- DDRSS_CTL_180[31-24]
MR14_DATA_F2_0
- DDRSS_CTL_187[31-24]
MR14_DATA_F0_1
- DDRSS_CTL_188[7-0]
MR14_DATA_F1_1
- DDRSS_CTL_188[15-8]
MR14_DATA_F2_1
- DDRSS_CTL_181[31-24]
MR22_DATA_F0_0
- DDRSS_CTL_182[7-0]
MR22_DATA_F1_0
- DDRSS_CTL_182[15-8]
MR22_DATA_F2_0
- DDRSS_CTL_189[15-8]
MR22_DATA_F0_1
- DDRSS_CTL_189[23-16]
MR22_DATA_F1_1
- DDRSS_CTL_189[31-24]
MR22_DATA_F2_1
In addition, the following fields must also be
programmed before asserting the DDRSS_CTL_0[0] START bit:
- DDRSS_CTL_165[25-16]
TFC_F0
- DDRSS_CTL_166[4-0]
TCKFSPE_F0
- DDRSS_CTL_166[12-8]
TCKFSPX_F0
- DDRSS_CTL_164[25-16]
TVRCG_ENABLE_F0
- DDRSS_CTL_165[9-0]
TVRCG_DISABLE_F0
- DDRSS_CTL_168[9-0]
TFC_F1
- DDRSS_CTL_168[20-16]
TCKFSPE_F1
- DDRSS_CTL_160[28-24]
TCKFSPX_F1
- DDRSS_CTL_167[9-0]
TVRCG_ENABLE_F1
- DDRSS_CTL_167[25-16]
TVRCG_DISABLE_F1
- DDRSS_CTL_170[25-16]
TFC_F2
- DDRSS_CTL_171[4-0]
TCKFSPE_F2
- DDRSS_CTL_171[12-8]
TCKFSPX_F2
- DDRSS_CTL_169[25-16]
TVRCG_ENABLE_F2
- DDRSS_CTL_170[9-0]
TVRCG_DISABLE_F2
- DDRSS_CTL_21[1-0]
DFIBUS_BOOT_FREQ
- DDRSS_CTL_20[25-24]
DFIBUS_FREQ_INIT
- DDRSS_CTL_149[24]
DFS_ENABLE
- DDRSS_CTL_191[24]
FSP_PHY_UPDATE_MRW
The following bits may or may not be modified, depending on what operations are needed after a frequency change occurs:
- DDRSS_CTL_192[0] DFS_ALWAYS_WRITE_FSP
- DDRSS_CTL_89[16] DFS_ZQ_EN
Once the DDRSS_CTL_0[0] START bit is asserted, the
DDR controller programs the mode registers in the memory devices with these values
using the FSP-OP and FSP-WR values from the DDRSS_CTL_180[7-0] MR13_DATA_0 field.
Once initialization is complete, either the PHY, PI, or controller will have updated
the frequency set points with the needed values.