SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The interrupt period is not exactly 1 ms, because the timer input clock is 32.768 kHz. If the clock counts up to 32, it obtains a 0.977-ms period; if it counts up to 33, it obtains a 1.007-ms period. For large granularity, the error is cumulative and can generate important deviations from the standard value.
To minimize the error between a true 1-ms tick and the tick generated by the 32.768-kHz timer, the sequencing of periods less than 1 ms and periods greater than 1 ms must be shuffled. An additional 1-ms block is used to correct this error. See Figure 12-527.
In this implementation, the increment sequencing is automatically managed by the timer to minimize the error. The user must define only the value of the timer positive increment register (the TIMER_TPIR[31-0] POSITIVE_INC_VALUE bit field) and the timer negative increment register (the TIMER_TNIR[31-0] NEGATIVE_INC_VALUE bit field). An automatic adaptation mechanism is used to simplify the programming model.
The TIMER_TPIR, TIMER_TNIR, and TIMER_TCVR registers and adders Add1, Add2, and Add3 are used to define whether the next value loaded in the timer counter register (the TIMER_TCRR[31-0] TIMER_COUNTER bit field) is the value of the TIMER_TLDR[31-0] LOAD_VALUE bit field (period less than 1 ms) or the value of TIMER_TLDR[31-0] LOAD_VALUE –1 (period greater than 1 ms).
Table 12-495 lists the value loaded in the TIMER_TCRR according to the sign of the result of Add1, Add2, and Add3.
MSB = 0: Positive value; MSB = 1: Negative value
Add1 MSB | Add2 MSB | Add3 MSB | Value of TIMER_TCRR Register |
---|---|---|---|
0 | 0 | 0 | TIMER_TLDR[31-0] LOAD_VALUE bit field |
0 | 0 | 1 | TIMER_TLDR[31-0] LOAD_VALUE bit field |
0 | 1 | 0 | TIMER_TLDR[31-0] LOAD_VALUE bit field |
0 | 1 | 1 | TIMER_TLDR[31-0] LOAD_VALUE –1 |
1 | 0 | 0 | N/A |
1 | 0 | 1 | N/A |
1 | 1 | 0 | TIMER_TLDR[31-0] LOAD_VALUE –1 |
1 | 1 | 1 | TIMER_TLDR[31-0] LOAD_VALUE –1 |
The values of the TIMER_TPIR and TIMER_TNIR registers are calculated using the following formulas:
Fclk clock frequency (kHz)
Ttick tick period (ms)
The timer overflow counter register (TIMER_TOCR) and the timer overflow wrapping register (TIMER_TOWR) are used to filter interrupts. When the timer overflows, it increments the 24-bit TIMER_TOCR. When the values in the 24-bit TIMER_TOCR match the values in the 24-bit TIMER_TOWR and the timer overflow is asserted, the TIMER_TOCR is reset and an interrupt is generated to the TIMER_IRQSTATUS register.
TIMER_TOWR has to be set to requested value. For example, if no interrupt needs to be masked TIMER_TOWR must be set to 0, if one interrupt needs to be masked TIMER_TOWR must be set to 1, if two interrupts need to be masked TIMER_TOWR must be set to 2 and so on.
It is important to have in mind that the case when FFFFFF interrupts need to be masked is not possible.
With the conversion block in reset state (the positive increment register, negative increment register, and counter value register are zeroed), the programming model and the behavior of timers remain unchanged.
For 1-ms tick with a 32.768-kHz clock:
Any value of the tick period can be generated with the appropriate value of the TIMER_TPIR, TIMER_TNIR, and TIMER_TLDR.
By default, the TIMER_TPIR, TIMER_TNIR, TIMER_TCVR, TIMER_TOCR, and TIMER_TOWR and the associated logic are in reset mode (all 0s) and have no effect on the programming model.