SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The pixel clocks going to the VPn as well as the pixel clocks going to the peripherals (Pn) will be different under different cases, depending on whether the output is in BYPASS, SYNC, MERGE or SPLIT mode. The different combinations of the clocks are as shown in Figure 12-411 and Figure 12-412.
Figure 12-412 show VP1 and VP2. Same clock scheme is applicable to VP3 and VP4.
For all cases in Figure 12-411 and Figure 12-412 there is no async interaction between P1_PCLKs and P2_PCLKs.