Each instance of the dual-core Arm Cortex-R5F
processor supports the following main features:
- Armv7-R architecture
- Two modes of operation,
boot-time configurable:
- Split mode: two
independently operating cores (asymmetric multi processing, no
coherence)
- Lock (lockstep) mode:
one main operating core with the other operating in lockstep
- Boot-time
configurable to be in split or lock mode
- 32KB instruction and 32KB
data SECDED ECC protected L1 cache per core
- 64KB of Tightly Coupled
Memory (TCM) per core in a split mode
- 128KB of TCM for CPU0 in lock
mode
- Full-Precision Floating Point
(VFPv3)
- 8 breakpoints, 8 watch
points
- 16-region Memory Protection
Unit (MPU)
- CoreSight Debug Access Port
(DAP)
- CoreSight ETM-R5
interface
- Performance Monitoring Unit
(PMU)
- 32-bit to 48-bit Region-based
Address Translation (RAT) on memory access masters
- Integrated Vectored Interrupt
Manager (VIM)
- Interfaces:
- 64-bit VBUSM master
pair (1 read, 1 write) for L3 memory accesses (per core)
- 64-bit VBUSM slave
for TCM access (per core)
- 32-bit VBUSM master
pair (1 read, 1 write) for peripheral access
- 32-bit VBUSP master
for peripheral access (per core)
- 32-bit VBUSP slave
configuration port (per core)
- 32-bit VBUSP slave
debug port