SPRUJ52C june   2022  – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Export Control Notice
    6.     Release History
    7.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
      1. 1.1.1 Device Overview Feature List
      2. 1.1.2 Device Block Diagram
      3. 1.1.3 Modules Allocation and Instances within Device Domains
    2. 1.2 Module Descriptions
      1. 1.2.1  Arm Cortex-A72 Subsystem
      2. 1.2.2  Arm Cortex-R5F Processor
      3. 1.2.3  C71x DSP Subsystem
      4. 1.2.4  Graphics Processing Unit
      5. 1.2.5  Video Accelerator
      6. 1.2.6  Vision Pre-processing Accelerator
      7. 1.2.7  Depth and Motion Perception Accelerator
      8. 1.2.8  Navigator Subsystem
      9. 1.2.9  Region-based Address Translation Module
      10. 1.2.10 Data Routing Unit
      11. 1.2.11 Display Subsystem
      12. 1.2.12 Camera Subsystem
      13. 1.2.13 Shared D-PHY Transmitter
      14. 1.2.14 Central Multicore Shared Memory Controller
      15. 1.2.15 Local C7/MMA Multicore Shared Memory Controller
      16. 1.2.16 DDR Subsystem
      17. 1.2.17 General Purpose Input/Output Interface
      18. 1.2.18 Inter-Integrated Circuit Interface
      19. 1.2.19 Improved Inter-Integrated Circuit Interface
      20. 1.2.20 Multi-channel Serial Peripheral Interface
      21. 1.2.21 Universal Asynchronous Receiver/Transmitter
      22. 1.2.22 Peripheral Component Interconnect Express Subsystem
      23. 1.2.23 Universal Serial Bus (USB) Subsystem
      24. 1.2.24 SerDes
      25. 1.2.25 General Purpose Memory Controller with Error Location Module
      26. 1.2.26 Multimedia Card/Secure Digital Interface
      27. 1.2.27 Universal Flash Storage Interface
      28. 1.2.28 Enhanced Capture Module
      29. 1.2.29 Enhanced Pulse-Width Modulation Module
      30. 1.2.30 Enhanced Quadrature Encoder Pulse Module
      31. 1.2.31 Controller Area Network
      32. 1.2.32 Audio Tracking Logic
      33. 1.2.33 Multi-channel Audio Serial Port
      34. 1.2.34 Timers
      35. 1.2.35 Internal Diagnostics Modules
      36. 1.2.36 Analog-to-Digital Converter
      37. 1.2.37 Two-Port Gigabit Ethernet Switch
      38. 1.2.38 Nine-Port Gigabit Ethernet Switch
      39. 1.2.39 Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      40. 1.2.40 Security Management Subsystem
    3. 1.3 Device Identification
  4. 2 Memory Maps
    1. 2.1 Memory Map
    2. 2.2 Memory Map
    3. 2.3 Memory Map
    4. 2.4 Processors View Memory Map
      1. 2.4.1 Memory Map
      2. 2.4.2 Memory Map
      3. 2.4.3 Memory Map
      4. 2.4.4 Memory Map
      5. 2.4.5 Memory Map
      6. 2.4.6 Memory Map
      7. 2.4.7 Memory Map
      8. 2.4.8 Memory Map
      9. 2.4.9 Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Functional Description
      1. 3.2.1 Quality of Service (QoS)
        1. 3.2.1.1  AEP_GPU_BXS464_WRAP0_QoS_Map
        2. 3.2.1.2  CODEC0_QoS_Map
        3. 3.2.1.3  CODEC1_QoS_Map
        4. 3.2.1.4  COMPUTE_CLUSTER0_QoS_Map
        5. 3.2.1.5  COMPUTE_CLUSTERHP0_QoS_Map
        6. 3.2.1.6  DEBUGSS_WRAP0_QoS_Map
        7. 3.2.1.7  DMPAC0_QoS_Map
        8. 3.2.1.8  DSS0_QoS_Map
        9. 3.2.1.9  MCU_NAVSS0_PROXY0_QoS_Map
        10. 3.2.1.10 MCU_NAVSS0_RINGACC0_QoS_Map
        11. 3.2.1.11 MCU_NAVSS0_SEC_PROXY0_QoS_Map
        12. 3.2.1.12 MCU_R5FSS0_QoS_Map
        13. 3.2.1.13 MCU_SA3_SS0_QoS_Map
        14. 3.2.1.14 MMCSD0_QoS_Map
        15. 3.2.1.15 MMCSD1_QoS_Map
        16. 3.2.1.16 NAVSS0_PROXY_0_QoS_Map
        17. 3.2.1.17 NAVSS0_SEC_PROXY_0_QoS_Map
        18. 3.2.1.18 PCIE0_QoS_Map
        19. 3.2.1.19 PCIE1_QoS_Map
        20. 3.2.1.20 PCIE2_QoS_Map
        21. 3.2.1.21 PCIE3_QoS_Map
        22. 3.2.1.22 R5FSS0_QoS_Map
        23. 3.2.1.23 R5FSS1_QoS_Map
        24. 3.2.1.24 R5FSS2_QoS_Map
        25. 3.2.1.25 SA2_UL0_QoS_Map
        26. 3.2.1.26 UFS0_QoS_Map
        27. 3.2.1.27 USB0_QoS_Map
        28. 3.2.1.28 VPAC0_QoS_Map
        29. 3.2.1.29 VPAC1_QoS_Map
        30. 3.2.1.30 VUSR_DUAL0_QoS_Map
        31. 3.2.1.31 WKUP_SMS0_QoS_Map
      2. 3.2.2 Route ID
      3. 3.2.3 Initiator-Side Security Controls and Firewalls
        1. 3.2.3.1 Initiator-Side Security Controls (ISC)
          1. 3.2.3.1.1  Special System Level Priv-ID
          2. 3.2.3.1.2  A72SS0_CORE0_0 ISC Table
          3. 3.2.3.1.3  A72SS0_CORE1_0 ISC Table
          4. 3.2.3.1.4  A72SS0_CORE2_0 ISC Table
          5. 3.2.3.1.5  A72SS0_CORE3_0 ISC Table
          6. 3.2.3.1.6  A72SS1_CORE0_0 ISC Table
          7. 3.2.3.1.7  A72SS1_CORE1_0 ISC Table
          8. 3.2.3.1.8  A72SS1_CORE2_0 ISC Table
          9. 3.2.3.1.9  A72SS1_CORE3_0 ISC Table
          10. 3.2.3.1.10 AEP_GPU_BXS464_WRAP0 ISC Table
          11. 3.2.3.1.11 CODEC0 ISC Table
          12. 3.2.3.1.12 CODEC1 ISC Table
          13. 3.2.3.1.13 COMPUTE_CLUSTER0 ISC Table
          14. 3.2.3.1.14 COMPUTE_CLUSTER0_C71SS0_0 ISC Table
          15. 3.2.3.1.15 COMPUTE_CLUSTER0_C71SS1_0 ISC Table
          16. 3.2.3.1.16 COMPUTE_CLUSTER0_C71SS2_0 ISC Table
          17. 3.2.3.1.17 COMPUTE_CLUSTER0_C71SS3_0 ISC Table
          18. 3.2.3.1.18 COMPUTE_CLUSTERHP0 ISC Table
          19. 3.2.3.1.19 COMPUTE_CLUSTERHP0_A72SS0_CORE0_0 ISC Table
          20. 3.2.3.1.20 COMPUTE_CLUSTERHP0_A72SS0_CORE1_0 ISC Table
          21. 3.2.3.1.21 COMPUTE_CLUSTERHP0_C71SS0_0 ISC Table
          22. 3.2.3.1.22 COMPUTE_CLUSTERHP0_C71SS1_0 ISC Table
          23. 3.2.3.1.23 DEBUGSS_WRAP0 ISC Table
          24. 3.2.3.1.24 DMPAC0_DOF_0 ISC Table
          25. 3.2.3.1.25 DMPAC0_FOCO_0 ISC Table
          26. 3.2.3.1.26 DMPAC0_FOCO_1 ISC Table
          27. 3.2.3.1.27 DMPAC0_SDE_0 ISC Table
          28. 3.2.3.1.28 DSS0 ISC Table
          29. 3.2.3.1.29 LED0 ISC Table
          30. 3.2.3.1.30 MCU_NAVSS0_PROXY0 ISC Table
          31. 3.2.3.1.31 MCU_NAVSS0_RINGACC0 ISC Table
          32. 3.2.3.1.32 MCU_NAVSS0_SEC_PROXY0 ISC Table
          33. 3.2.3.1.33 MCU_R5FSS0 ISC Table
          34. 3.2.3.1.34 MCU_SA3_SS0 ISC Table
          35. 3.2.3.1.35 MMCSD0 ISC Table
          36. 3.2.3.1.36 MMCSD1 ISC Table
          37. 3.2.3.1.37 NAVSS0_PROXY_0 ISC Table
          38. 3.2.3.1.38 NAVSS0_RINGACC_0 ISC Table
          39. 3.2.3.1.39 NAVSS0_SEC_PROXY_0 ISC Table
          40. 3.2.3.1.40 PCIE0 ISC Table
          41. 3.2.3.1.41 PCIE1 ISC Table
          42. 3.2.3.1.42 PCIE2 ISC Table
          43. 3.2.3.1.43 PCIE3 ISC Table
          44. 3.2.3.1.44 R5FSS0 ISC Table
          45. 3.2.3.1.45 R5FSS1 ISC Table
          46. 3.2.3.1.46 R5FSS2 ISC Table
          47. 3.2.3.1.47 SA2_UL0 ISC Table
          48. 3.2.3.1.48 UFS0 ISC Table
          49. 3.2.3.1.49 USB0 ISC Table
          50. 3.2.3.1.50 VPAC0 ISC Table
          51. 3.2.3.1.51 VPAC1 ISC Table
          52. 3.2.3.1.52 WKUP_SMS0_HSM_CBASS_0 ISC Table
          53. 3.2.3.1.53 WKUP_SMS0_TIFS_CBASS_0 ISC Table
      4. 3.2.4 Firewalls (FW)
        1. 3.2.4.1 Peripheral Firewalls (FW)
        2. 3.2.4.2 Memory or Region-based Firewalls
          1. 3.2.4.2.1 Region Based Firewall Functional Description
          2. 3.2.4.2.2 Channelized Firewalls
            1. 3.2.4.2.2.1 Channelized Firewall Functional Description
      5. 3.2.5 Null Error Reporting
      6. 3.2.6 Initiator-Target Connections
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 SMS ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  xSPI-Fast Boot Mode Configuration
      10. 4.3.10 I2C Boot Device Configuration
      11. 4.3.11 MMC/SD Card Boot Device Configuration
      12. 4.3.12 eMMC Boot Device Configuration
      13. 4.3.13 Ethernet Boot Device Configuration
      14. 4.3.14 USB Boot Device Configuration
      15. 4.3.15 PCIe Boot Device Configuration
      16. 4.3.16 UART Boot Device Configuration
      17. 4.3.17 Serial NAND Boot Device Configuration
      18. 4.3.18 PLL Configuration
        1. 4.3.18.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.18.2 MCU_PLL1
        3. 4.3.18.3 Main PLL1
        4. 4.3.18.4 Main PLL2
        5. 4.3.18.5 HSDIV Values
        6. 4.3.18.6 216
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  xSPI/Fast-xSPI Boot Parameter Table
      7. 4.4.7  Ethernet Boot Parameter Table
      8. 4.4.8  USB Boot Parameter Table
      9. 4.4.9  MMCSD Boot Parameter Table
      10. 4.4.10 UART Boot Parameter Table
      11. 4.4.11 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 253
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 CTRL_MMR Overview
      2. 5.1.2 CTRL_MMR Functional Description
        1. 5.1.2.1  Register Partitions
        2. 5.1.2.2  Pad Configuration Registers
        3. 5.1.2.3  Kick Protection Registers
        4. 5.1.2.4  Proxy Addressing Registers
        5. 5.1.2.5  CTRL_MMR Interrupts
        6. 5.1.2.6  Inter-processor Communication Registers
        7. 5.1.2.7  Timer IO Muxing Control Registers
        8. 5.1.2.8  EHRPWM/EQEP Control and Status Registers
        9. 5.1.2.9  Clock Muxing and Division Registers
        10. 5.1.2.10 Module Control Registers
        11. 5.1.2.11 DDRSS Dynamic Frequency Change Registers
        12. 5.1.2.12 MAC Address Registers
        13. 5.1.2.13 Feature Registers
        14. 5.1.2.14 Power and Reset Related Registers
        15. 5.1.2.15 I/O Debounce Control Registers
      3. 5.1.3 Control Module Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 WKUP_PSC0 Device-Specific Information
      3. 5.2.3 Power Management Subsystems
        1. 5.2.3.1 Power Subsystems Overview
          1. 5.2.3.1.1 POK Overview
          2. 5.2.3.1.2 PRG / PRG_PP Overview
          3. 5.2.3.1.3 POR Overview
          4. 5.2.3.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.3.1.5 Timing
          6. 5.2.3.1.6 Restrictions
        2. 5.2.3.2 Power System Modules
          1. 5.2.3.2.1 Power OK (POK) Modules
            1. 5.2.3.2.1.1 POK Programming Model
          2. 5.2.3.2.2 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.3.2.2.1 PRG_PP Overview
            2. 5.2.3.2.2.2 PRG_PP Programming Model
          3. 5.2.3.2.3 Power Glitch Detect (PGD) Modules
          4. 5.2.3.2.4 Voltage and Thermal Manager (VTM)
            1. 5.2.3.2.4.1 VTM Overview
              1. 5.2.3.2.4.1.1 VTM Features
              2. 5.2.3.2.4.1.2 VTM Not Supported Features
            2. 5.2.3.2.4.2 VTM Functional Description
              1. 5.2.3.2.4.2.1 VTM Temperature Status and Thermal Management
                1. 5.2.3.2.4.2.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.3.2.4.2.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.3.2.4.2.3 VTM ECC Aggregator
              4. 5.2.3.2.4.2.4 VTM Programming Model
                1. 5.2.3.2.4.2.4.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.3.2.4.2.4.2 Sensors Programming Sequences
              5. 5.2.3.2.4.2.5 AVS-Class0
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Modules
      3. 5.3.3 Reset Sources
      4. 5.3.4 Reset Status
      5. 5.3.5 Reset Control
      6. 5.3.6 BOOTMODE Pins
      7. 5.3.7 Reset Sequences
        1. 5.3.7.1 MCU_PORz Overview
        2. 5.3.7.2 MCU_PORz Sequence
        3. 5.3.7.3 MCU_RESETz Sequence
        4. 5.3.7.4 PORz Sequence
        5. 5.3.7.5 RESET_REQz Sequence
      8. 5.3.8 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Clocking Overview
      2. 5.4.2 Modules Controlled by PLL
      3. 5.4.3 Clock Mapping
      4. 5.4.4 Overview
      5. 5.4.5 Clock Inputs
        1. 5.4.5.1 Overview
        2. 5.4.5.2 Mapping of Clock Inputs
      6. 5.4.6 Clock Outputs
        1. 5.4.6.1 Observation Clock Pins
          1. 5.4.6.1.1 MCU_OBSCLK0 Pin
          2. 5.4.6.1.2 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.6.2 System Clock Pins
          1. 5.4.6.2.1 MCU_SYSCLKOUT0
          2. 5.4.6.2.2 SYSCLKOUT0
      7. 5.4.7 Device Oscillators
        1. 5.4.7.1 Device Oscillators Integration
          1. 5.4.7.1.1 Oscillators with External Crystal
          2. 5.4.7.1.2 Internal RC Oscillator
        2. 5.4.7.2 Oscillator Clock Loss Detection
      8. 5.4.8 PLLs
        1. 5.4.8.1  WKUP and MCU Domains PLL Overview
        2. 5.4.8.2  MAIN Domain PLLs Overview
        3. 5.4.8.3  PLL Reference Clocks
          1. 5.4.8.3.1 PLLs in MCU Domain
          2. 5.4.8.3.2 PLLs in MAIN Domain
        4. 5.4.8.4  Generic PLL Overview
          1. 5.4.8.4.1 PLLs Output Clocks Parameters
            1. 5.4.8.4.1.1 PLLs Input Clocks
            2. 5.4.8.4.1.2 PLL Output Clocks
              1. 5.4.8.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.8.4.1.2.2 PLL Lock
              3. 5.4.8.4.1.2.3 HSDIVIDER
              4. 5.4.8.4.1.2.4 ICG Module
              5. 5.4.8.4.1.2.5 PLL Power Down
              6. 5.4.8.4.1.2.6 PLL Calibration
          2. 5.4.8.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.8.4.2.1 Definition of SSMOD
            2. 5.4.8.4.2.2 SSMOD Configuration
        5. 5.4.8.5  PLLs Device-Specific Information
          1. 5.4.8.5.1 SSMOD Related Bitfields Table
          2. 5.4.8.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.8.5.3 Clock Output Parameter
          4. 5.4.8.5.4 Calibration Related Bitfields
        6. 5.4.8.6  PLL and PLL Controller Connection
        7. 5.4.8.7  System Clocks Operating Frequency Ranges
        8. 5.4.8.8  Recommended Clock and Control Signal Transition Behavior
        9. 5.4.8.9  Interface Clock Specifications
        10. 5.4.8.10 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.8.10.1 PLL Initialization
            1. 5.4.8.10.1.1 Kick Protection Mechanism
            2. 5.4.8.10.1.2 PLL Initialization to PLL Mode
            3. 5.4.8.10.1.3 PLL Programming Requirements
              1. 5.4.8.10.1.3.1 PLL Calibration Procedure
          2. 5.4.8.10.2 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
    5. 5.5 Module Integration
      1. 5.5.1  ADC
        1. 5.5.1.1 ADC Unsupported Features
        2. 5.5.1.2 ADC Integration Details
      2. 5.5.2  ATL
        1. 5.5.2.1 ATL Unsupported Features
        2. 5.5.2.2 ATL Integration Details
      3. 5.5.3  CPSW2G
        1. 5.5.3.1 CPSW2G Unsupported Features
        2. 5.5.3.2 MCU_CPSW2G0 Integration Details
        3. 5.5.3.3 CPSW2G0 Integration Details
      4. 5.5.4  CPSW9G
        1. 5.5.4.1 CPSW9G0 Unsupported Features
        2. 5.5.4.2 CPSW9G0 Integration Details
      5. 5.5.5  CSI_RX
        1. 5.5.5.1 CSI_RX Unsupported Features
        2. 5.5.5.2 CSI_RX Integration Details
      6. 5.5.6  CSI_TX
        1. 5.5.6.1 CSI_TX Unsupported Features
        2. 5.5.6.2 CSI_TX Integration Details
      7. 5.5.7  DCC
        1. 5.5.7.1 DCC Unsupported Features
        2. 5.5.7.2 DCC Integration Details
      8. 5.5.8  DMTIMER (Timer)
        1. 5.5.8.1 DMTIMER (Timer) Unsupported Features
        2. 5.5.8.2 DMTIMER (Timer) Integration Details
      9. 5.5.9  DPHY_RX
        1. 5.5.9.1 DPHY_RX Unsupported Features
        2. 5.5.9.2 DPHY_RX Integration Details
      10. 5.5.10 DPHY_TX
        1. 5.5.10.1 DPHY_TX Unsupported Features
        2. 5.5.10.2 DPHY_TX Integration Details
      11. 5.5.11 DSS/DSI
        1. 5.5.11.1 DSS Unsupported Features
        2. 5.5.11.2 DSI Unsupported Features
        3. 5.5.11.3 DSS/DSI Integration Details
          1. 5.5.11.3.1 DSS Pixel Clock Sourcing
      12. 5.5.12 eCAP
        1. 5.5.12.1 eCAP Unsupported Features
        2. 5.5.12.2 eCAP Integration Details
      13. 5.5.13 ePWM
        1. 5.5.13.1 ePWM Unsupported Features
        2. 5.5.13.2 ePWM Integration Details
      14. 5.5.14 ESM
        1. 5.5.14.1 ESM Unsupported Features
        2. 5.5.14.2 ESM Integration Details
      15. 5.5.15 FSS
        1. 5.5.15.1 FSS Unsupported Features
        2. 5.5.15.2 FSS Integration Details
      16. 5.5.16 GPIO
        1. 5.5.16.1 GPIO Unsupported Features
        2. 5.5.16.2 GPIO Integration Details
      17. 5.5.17 GPMC
        1. 5.5.17.1 GPMC Unsupported Features
        2. 5.5.17.2 GPMC Integration Details
      18. 5.5.18 GPU
        1. 5.5.18.1 GPU Unsupported Features
        2. 5.5.18.2 GPU Integration Details
      19. 5.5.19 I2C
        1. 5.5.19.1 WKUP_I2C0 Unsupported Features
        2. 5.5.19.2 MCU_I2C[1:0] Unsupported Features
        3. 5.5.19.3 I2C[6:0] Unsupported Features
        4. 5.5.19.4 I2C Integration Details
      20. 5.5.20 I3C
        1. 5.5.20.1 I3C Unsupported Features
        2. 5.5.20.2 I3C Integration Details
      21. 5.5.21 MCAN
        1. 5.5.21.1 MCAN Unsupported Features
        2. 5.5.21.2 MCAN Integration Details
      22. 5.5.22 MMCSD
        1. 5.5.22.1 MMCSD Unsupported Features
        2. 5.5.22.2 MMCSD Integration Details
      23. 5.5.23 McASP
        1. 5.5.23.1 McASP Unsupported Features
        2. 5.5.23.2 McASP Integration Details
      24. 5.5.24 McSPI
        1. 5.5.24.1 MCSPI Unsupported Features
        2. 5.5.24.2 MCSPI Integration Details
      25. 5.5.25 PCIE
        1. 5.5.25.1 PCIE Unsupported Features
        2. 5.5.25.2 PCIE Integration Details
      26. 5.5.26 R5FSS
        1. 5.5.26.1 R5FSS and MCU_R5FSS Unsupported Features
        2. 5.5.26.2 MCU_R5FSS Integration Details
        3. 5.5.26.3 R5FSS Integration Details
      27. 5.5.27 RAT
        1. 5.5.27.1 RAT Integration Details
          1. 5.5.27.1.1 RAT Source IDs
      28. 5.5.28 RTI
        1. 5.5.28.1 RTI Unsupported Features
        2. 5.5.28.2 RTI Integration Details
      29. 5.5.29 UART
        1. 5.5.29.1 UART Unsupported Features
        2. 5.5.29.2 UART Integration Details
      30. 5.5.30 UFS
        1. 5.5.30.1 UFS Unsupported Features
        2. 5.5.30.2 UFS Integration Details
      31. 5.5.31 USBSS
        1. 5.5.31.1 USB Unsupported Features
        2. 5.5.31.2 USB Integration Details
      32. 5.5.32 Video CODEC
        1. 5.5.32.1 CODEC Unsupported Features
        2. 5.5.32.2 CODEC Integration Details
      33. 5.5.33 VPAC
        1. 5.5.33.1 VPAC Unsupported Features
        2. 5.5.33.2 VPAC Integration Details
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
    2. 6.2 Quad-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Functional Description
        1. 6.2.2.1  A72SS Block Diagram
        2. 6.2.2.2  A72SS A72 Cluster
        3. 6.2.2.3  A72SS Interfaces and Async Bridges
        4. 6.2.2.4  A72SS Interrupts
          1. 6.2.2.4.1 A72SS Interrupt Inputs
          2. 6.2.2.4.2 A72SS Interrupt Outputs
        5. 6.2.2.5  A72SS Power Management, Clocking and Reset
          1. 6.2.2.5.1 A72SS Power Management
          2. 6.2.2.5.2 A72SS Clocking
        6. 6.2.2.6  A72SS Debug Support
        7. 6.2.2.7  A72SS Timestamps
        8. 6.2.2.8  A72SS Watchdog
        9. 6.2.2.9  A72SS Internal Diagnostics
          1. 6.2.2.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.2.9.2 A72SS CBASS Diagnostics
          3. 6.2.2.9.3 A72SS SRAM Diagnostics
          4. 6.2.2.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.2.10 A72SS Boot
        11. 6.2.2.11 A72SS IPC with Other CPUs
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
      2. 6.3.2 R5FSS Functional Description
        1. 6.3.2.1  R5FSS Block Diagram
        2. 6.3.2.2  R5FSS Cortex-R5F Core
          1. 6.3.2.2.1 L1 Caches
          2. 6.3.2.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.2.2.3 R5FSS Special Signals
        3. 6.3.2.3  R5FSS Interfaces
          1. 6.3.2.3.1 R5FSS Master Interfaces
          2. 6.3.2.3.2 R5FSS Slave Interfaces
        4. 6.3.2.4  R5FSS Power, Clocking and Reset
          1. 6.3.2.4.1 R5FSS Power
          2. 6.3.2.4.2 R5FSS Clocking
            1. 6.3.2.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.2.4.3 R5FSS Reset
        5. 6.3.2.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.2.5.1 CPU Output Compare Block
            1. 6.3.2.5.1.1 Operating Modes
            2. 6.3.2.5.1.2 Compare Block Active Mode
            3. 6.3.2.5.1.3 Self Test Mode
            4. 6.3.2.5.1.4 Compare Match Test
            5. 6.3.2.5.1.5 Compare Mismatch Test
            6. 6.3.2.5.1.6 Error Forcing Mode
            7. 6.3.2.5.1.7 Self Test Error Forcing Mode
          2. 6.3.2.5.2 Inactivity Monitor Block
            1. 6.3.2.5.2.1 Operating Modes
            2. 6.3.2.5.2.2 Compare Block Active Mode
            3. 6.3.2.5.2.3 Self Test Mode
            4. 6.3.2.5.2.4 Compare Match Test
            5. 6.3.2.5.2.5 Compare Mismatch Test
            6. 6.3.2.5.2.6 Error Forcing Mode
            7. 6.3.2.5.2.7 Self Test Error Forcing Mode
          3. 6.3.2.5.3 Polarity Inversion Logic
        6. 6.3.2.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.2.6.1 VIM Overview
          2. 6.3.2.6.2 VIM Interrupt Inputs
          3. 6.3.2.6.3 VIM Interrupt Outputs
          4. 6.3.2.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.2.6.5 VIM Interrupt Prioritization
          6. 6.3.2.6.6 VIM ECC Support
          7. 6.3.2.6.7 VIM Lockstep Mode
          8. 6.3.2.6.8 VIM IDLE State
          9. 6.3.2.6.9 VIM Interrupt Handling
            1. 6.3.2.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.2.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.2.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.2.6.9.4 Servicing FIQ
            5. 6.3.2.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.2.7  R5FSS Region Address Translation (RAT)
          1. 6.3.2.7.1 RAT Overview
          2. 6.3.2.7.2 RAT Operation
          3. 6.3.2.7.3 RAT Error Logging
          4. 6.3.2.7.4 RAT Protection
        8. 6.3.2.8  R5FSS ECC Support
        9. 6.3.2.9  R5FSS Memory View
        10. 6.3.2.10 R5FSS Debug and Trace
        11. 6.3.2.11 R5FSS Boot Options
        12. 6.3.2.12 R5FSS Core Memory ECC Events
    4. 6.4 C71x DSP Subsystem
      1. 6.4.1 C71SS Overview
        1. 6.4.1.1 C71SS Features
      2. 6.4.2 C71SS Functional Description
        1. 6.4.2.1 C71x DSP CPU
        2. 6.4.2.2 C71x DSP Matrix Multiply Accelerator
        3. 6.4.2.3 C71x DSP Cache Memory System
          1. 6.4.2.3.1 C71x DSP L1 Program Memory
          2. 6.4.2.3.2 C71x DSP L1 Data Memory
          3. 6.4.2.3.3 C71x DSP L2 Memory
        4. 6.4.2.4 C71x DSP Streaming Engine
        5. 6.4.2.5 C71x DSP CorePac Memory Management Unit
        6. 6.4.2.6 C71x DSP ECC Support
        7. 6.4.2.7 C71x DSP Boot Configuration
        8. 6.4.2.8 C71x DSP Power-Up/Down Sequences
        9. 6.4.2.9 C71x DSP Interrupt Control
    5. 6.5 Graphics Accelerator (GPU)
      1. 6.5.1 GPU Overview
      2. 6.5.2 Features Supported
    6. 6.6 Video Accelerator
      1. 6.6.1 Introduction
      2. 6.6.2 Features
        1. 6.6.2.1 Performance
        2. 6.6.2.2 Codec Related Features
        3. 6.6.2.3 Non-Codec Related Features
      3. 6.6.3 Block Diagram
    7. 6.7 Vision Pre-processing Accelerator (VPAC)
      1. 6.7.1 VPAC Overview
        1. 6.7.1.1 VPAC Features
      2. 6.7.2 VPAC Subsystem Level
        1. 6.7.2.1  VPAC Subsystem Block Diagram
          1. 6.7.2.1.1 Notes on VISS RFE H3A Usage
        2. 6.7.2.2  VPAC Subsystem Clocks
        3. 6.7.2.3  VPAC Subsystem Resets
        4. 6.7.2.4  VPAC Subsystem Interrupts
        5. 6.7.2.5  VPAC Subsystem SL2 Memory Infrastructure
        6. 6.7.2.6  VPAC Subsystem DMA Infrastructure
        7. 6.7.2.7  VPAC Subsystem Data Routing Interconnect
        8. 6.7.2.8  VPAC Subsystem Pipeline Flow Control and Messaging
          1. 6.7.2.8.1 VISS Node Scheduler
          2. 6.7.2.8.2 LDC Node Scheduler
          3. 6.7.2.8.3 MSC Node Scheduler
          4. 6.7.2.8.4 NF Node Scheduler
          5. 6.7.2.8.5 Spare Scheduler
        9. 6.7.2.9  VPAC Subsystem Data Formats Support
        10. 6.7.2.10 VPAC Subsystem Debug Features
        11. 6.7.2.11 VPAC Subsystem Internal Diagnostic Features
          1. 6.7.2.11.1 Parallel Signature Analysis (PSA)
        12. 6.7.2.12 VPAC Subsystem Security Features
        13. 6.7.2.13 VPAC Subsystem Programmer’s Guide
          1. 6.7.2.13.1 Initialization Sequence
          2. 6.7.2.13.2 VISS Configuration
            1. 6.7.2.13.2.1 VISS UTC Configuration
            2. 6.7.2.13.2.2 VISS HTS Configuration for Line Mode
            3. 6.7.2.13.2.3 VISS HTS Configuration for Frame Mode
          3. 6.7.2.13.3 VISS OTF Configuration
          4. 6.7.2.13.4 LDC Configuration (LDC Connected to MSC0, NF and DMA)
            1. 6.7.2.13.4.1 LDC DMA Configuration
            2. 6.7.2.13.4.2 LDC HTS Configuration
          5. 6.7.2.13.5 Real-time Operating Requirements
      3. 6.7.3 VPAC Vision Imaging Subsystem (VISS)
        1. 6.7.3.1 VISS Top Level
          1. 6.7.3.1.1  Features Supported
          2. 6.7.3.1.2  VISS Block Diagram
          3. 6.7.3.1.3  VISS Data Flow within VPAC
            1. 6.7.3.1.3.1 VISS On-the-fly Processing
              1. 6.7.3.1.3.1.1 Non-WDR or Companded WDR Sensors
            2. 6.7.3.1.3.2 VISS Memory to Memory Image Processing
          4. 6.7.3.1.4  Concurret Machine Vision and Human Vision Output
          5. 6.7.3.1.5  VISS Clocking
          6. 6.7.3.1.6  VISS Data Formats Support
          7. 6.7.3.1.7  VISS VPORT Interface
          8. 6.7.3.1.8  VISS Submodule Integration Specifics
            1. 6.7.3.1.8.1 LSE Integration
            2. 6.7.3.1.8.2 Chromatic Aberration Correction
            3. 6.7.3.1.8.3 Spatial Noise Filter (NSF4V)
            4. 6.7.3.1.8.4 GLBCE Integration
              1. 6.7.3.1.8.4.1 GLBCE Startup
              2. 6.7.3.1.8.4.2 GLBCE Bypass
            5. 6.7.3.1.8.5 Flexible Color Processing (FCP)
          9. 6.7.3.1.9  VISS Stall Handling
          10. 6.7.3.1.10 VISS Blanking Requirements
          11. 6.7.3.1.11 FCP2 Sync FIFO
          12. 6.7.3.1.12 VISS Interrupts
            1. 6.7.3.1.12.1 Interrupts Merging
            2. 6.7.3.1.12.2 Handling of Configuration Error Interrupts
          13. 6.7.3.1.13 VISS Error Correcting Code (ECC) Support
          14. 6.7.3.1.14 VISS Programmer's Guide
            1. 6.7.3.1.14.1 VISS Initialization Sequence
            2. 6.7.3.1.14.2 VISS Configuration Restrictions
            3. 6.7.3.1.14.3 VISS Real-time Operating Requirements
        2. 6.7.3.2 VISS RAW Frond-End (RAWFE)
          1. 6.7.3.2.1 RAWFE Overview
            1. 6.7.3.2.1.1 RAWFE Supported Features
            2. 6.7.3.2.1.2 RAWFE Not Supported Features
          2. 6.7.3.2.2 RAWFE Functional Description
            1. 6.7.3.2.2.1 RAWFE Functional Operation
            2. 6.7.3.2.2.2 RAWFE Integration in VISS
            3. 6.7.3.2.2.3 RAWFE Memory Map
            4. 6.7.3.2.2.4 RAWFE ECC for RAMs
          3. 6.7.3.2.3 RAWFE Interrupts
            1. 6.7.3.2.3.1 RAWFE CPU Interrupts
            2. 6.7.3.2.3.2 RAWFE Debug Events
            3. 6.7.3.2.3.3 RAWFE Interrupt Handling: High Priority
            4. 6.7.3.2.3.4 RAWFE Interrupt Handling: Low Priority
          4. 6.7.3.2.4 RAWFE Sub-Modules Details
            1. 6.7.3.2.4.1 RAWFE Decompanding Block
              1. 6.7.3.2.4.1.1 RAWFE Mask & Shift
              2. 6.7.3.2.4.1.2 RAWFE Piece Wise Linear Operation
              3. 6.7.3.2.4.1.3 RAWFE Offset/WB-1 Block
              4. 6.7.3.2.4.1.4 RAWFE LUT Based compression
            2. 6.7.3.2.4.2 RAWFE WDR Merge Block
              1. 6.7.3.2.4.2.1 RAWFE WDR Motion Adaptive Merge (MA1 / MA2)
              2. 6.7.3.2.4.2.2 RAWFE Companding LUT
            3. 6.7.3.2.4.3 RAWFE Defective Pixel Correction (DPC) Block
              1. 6.7.3.2.4.3.1 RAWFE LUT Based DPC
              2. 6.7.3.2.4.3.2 RAWFE On-The-Fly (OTF) DPC
            4. 6.7.3.2.4.4 RAWFE Lens Shading Correction (LSC) and Digital Gain (DG) Block
              1. 6.7.3.2.4.4.1 RAWFE LSC Features Supported
              2. 6.7.3.2.4.4.2 RAWFE LSC Image Framing with Respect to Gain Map Samples
            5. 6.7.3.2.4.5 RAWFE Gain & Offset Block
            6. 6.7.3.2.4.6 RAWFE H3A
              1. 6.7.3.2.4.6.1  RAWFE H3A Overview
              2. 6.7.3.2.4.6.2  RAWFE H3A Top-Level Block Diagram
              3. 6.7.3.2.4.6.3  RAWFE H3A Line Framing Logic
              4. 6.7.3.2.4.6.4  RAWFE H3A Optional Preprocessing
              5. 6.7.3.2.4.6.5  RAWFE H3A Autofocus Engine
                1. 6.7.3.2.4.6.5.1 RAWFE H3A Paxel Extraction
                2. 6.7.3.2.4.6.5.2 RAWFE H3A Horizontal FV Calculator
                3. 6.7.3.2.4.6.5.3 RAWFE H3A HFV Accumulator
                4. 6.7.3.2.4.6.5.4 RAWFE H3A VFV Calculator
                5. 6.7.3.2.4.6.5.5 RAWFE H3A VFV Accumulator
              6. 6.7.3.2.4.6.6  RAWFE H3A AE/AWB Engine
                1. 6.7.3.2.4.6.6.1 RAWFE H3A Subsampler
                2. 6.7.3.2.4.6.6.2 RAWFE H3A Additional Black Row of AE/AWB Windows
                3. 6.7.3.2.4.6.6.3 RAWFE H3A Saturation Check
                4. 6.7.3.2.4.6.6.4 RAWFE H3A AE/AWB Accumulators
              7. 6.7.3.2.4.6.7  RAWFE H3A DMA Interface
              8. 6.7.3.2.4.6.8  RAWFE H3A Events and Status Checking
              9. 6.7.3.2.4.6.9  RAWFE H3A Interface Mux
              10. 6.7.3.2.4.6.10 RAWFE H3A interface to LSE
              11. 6.7.3.2.4.6.11 RAWFE H3A Erratas
          5. 6.7.3.2.5 RAWFE Programmer’s Guide
            1. 6.7.3.2.5.1 RAWFE Core programming details
            2. 6.7.3.2.5.2 RAWFE HTS programming details
            3. 6.7.3.2.5.3 RAWFE Data transfer programming details
            4. 6.7.3.2.5.4 RAWFE Initialization Sequence
            5. 6.7.3.2.5.5 RAWFE Real-time Оperating Requirements
            6. 6.7.3.2.5.6 RAWFE Power up/down Sequence
        3. 6.7.3.3 Chromatic Aberration Correction (CAC) Module
          1. 6.7.3.3.1 Overview and Feature List
            1. 6.7.3.3.1.1 Features Supported
          2. 6.7.3.3.2 Functional Description
            1. 6.7.3.3.2.1 CAC Integration in VISS
            2. 6.7.3.3.2.2 Introduction
            3. 6.7.3.3.2.3 Functional Operation
              1. 6.7.3.3.2.3.1 CAC Back Mapping
                1. 6.7.3.3.2.3.1.1 Offset Table Storage Format
              2. 6.7.3.3.2.3.2 Pixel Interpolation
              3. 6.7.3.3.2.3.3 Bi-cubic Coefficients
            4. 6.7.3.3.2.4 Interrupt Conditions
              1. 6.7.3.3.2.4.1 Interrupts
              2. 6.7.3.3.2.4.2 Debug Events
        4. 6.7.3.4 VISS Spatial Noise Filter (NSF4V)
          1. 6.7.3.4.1 NSF4V Introduction
            1. 6.7.3.4.1.1 NSF4V Features
          2. 6.7.3.4.2 NSF4V Overview
            1. 6.7.3.4.2.1 Decomposition Kernel Representation
          3. 6.7.3.4.3 NSF4V Lens Shading Correction Compensation
          4. 6.7.3.4.4 NSF4V Noise Threshold Adaptation to Local Image Intensity
          5. 6.7.3.4.5 Delta Features
        5. 6.7.3.5 VISS Global/Local Brightness and Contrast Enhancement (GLBCE) Module
          1. 6.7.3.5.1 GLBCE Overview
          2. 6.7.3.5.2 GLBCE Interface
          3. 6.7.3.5.3 GLBCE Core
            1. 6.7.3.5.3.1 GLBCE Core Key Parameters
            2. 6.7.3.5.3.2 GLBCE Iridix Strength Calculation
            3. 6.7.3.5.3.3 GLBCE Iridix Configuration Registers
              1. 6.7.3.5.3.3.1  GLBCE Iridix Frame Width
              2. 6.7.3.5.3.3.2  GLBCE Iridix Frame Height
              3. 6.7.3.5.3.3.3  GLBCE Iridix Control 0
              4. 6.7.3.5.3.3.4  GLBCE Iridix Control 1
              5. 6.7.3.5.3.3.5  GLBCE Iridix Strength
              6. 6.7.3.5.3.3.6  GLBCE Iridix Variance
              7. 6.7.3.5.3.3.7  GLBCE Iridix Dither
              8. 6.7.3.5.3.3.8  GLBCE Iridix Amplification Limit
              9. 6.7.3.5.3.3.9  GLBCE Iridix Slope Min and Max
              10. 6.7.3.5.3.3.10 GLBCE Iridix Black Level
              11. 6.7.3.5.3.3.11 GLBCE Iridix White Level
              12. 6.7.3.5.3.3.12 GLBCE Iridix Asymmetry Function Look-up-table
              13. 6.7.3.5.3.3.13 GLBCE Iridix Forward and Reverse Perceptual Functions Look-up-tables
              14. 6.7.3.5.3.3.14 GLBCE Iridix WDR Look-up-table
          4. 6.7.3.5.4 GLBCE Embedded Memory
          5. 6.7.3.5.5 GLBCE General Processing
          6. 6.7.3.5.6 GLBCE Continuous Frame Processing
          7. 6.7.3.5.7 GLBCE Single Image Processing
        6. 6.7.3.6 VISS Flexible Color Processing (FCP) Module
          1. 6.7.3.6.1 FCP Overview
            1. 6.7.3.6.1.1 FCP Features Supported
          2. 6.7.3.6.2 FCP Functional Description
          3. 6.7.3.6.3 FCP Submodule Details
            1. 6.7.3.6.3.1 Flexible CFA / Demosaicing
              1. 6.7.3.6.3.1.1 Feature-set
              2. 6.7.3.6.3.1.2 Block Diagram of Flexible CFA
                1. 6.7.3.6.3.1.2.1 Gradient/Threshold Calculation
                2. 6.7.3.6.3.1.2.2 Software Controlled Direction Selection
              3. 6.7.3.6.3.1.3 Example Filter Coefficients - Green Interpolation
                1. 6.7.3.6.3.1.3.1 Example Filter Coefficients - Red/Blue Interpolation
              4. 6.7.3.6.3.1.4 CFA 16-Bit Upgrade
              5. 6.7.3.6.3.1.5 FIR Filter Output Scaling
              6. 6.7.3.6.3.1.6 Decopanding, 24-bit Color Conversion Matrix and Companding Blocks
                1. 6.7.3.6.3.1.6.1 The DcmpdLUT Block
                2. 6.7.3.6.3.1.6.2 The CCM Block
                3. 6.7.3.6.3.1.6.3 The CmpdLUT Block
                4. 6.7.3.6.3.1.6.4 Controls for the Decompanding, CCM, and Companding Blocks
                5. 6.7.3.6.3.1.6.5 Example Use Cases
            2. 6.7.3.6.3.2 Edge Enhancer Module Wrapper (WEE)
              1. 6.7.3.6.3.2.1 Align 12 Block
              2. 6.7.3.6.3.2.2 Align 8 Block
              3. 6.7.3.6.3.2.3 Mux Blocks
              4. 6.7.3.6.3.2.4 SL - Shift Left Block
              5. 6.7.3.6.3.2.5 EE - Edge Enhancer Block
              6. 6.7.3.6.3.2.6 SR - Shift Right Block
              7. 6.7.3.6.3.2.7 Edge Enhancer Module Wrapper (WEE) Registers
            3. 6.7.3.6.3.3 Flexible Color Conversion (CC)
              1. 6.7.3.6.3.3.1 Interface Mux
              2. 6.7.3.6.3.3.2 Color Conversion (CCM-1)
              3. 6.7.3.6.3.3.3 RGB to HSX Conversion
                1. 6.7.3.6.3.3.3.1 Weighted Average Block
                2. 6.7.3.6.3.3.3.2 Saturation Block
                3. 6.7.3.6.3.3.3.3 Division Block
                4. 6.7.3.6.3.3.3.4 LUT Based 12 to 8 Downsampling
              4. 6.7.3.6.3.3.4 Histogram
              5. 6.7.3.6.3.3.5 Contrast Stretch / Gamma
              6. 6.7.3.6.3.3.6 RGB-YUV Conversion
            4. 6.7.3.6.3.4 444-422/420 Chroma Down-sampler
            5. 6.7.3.6.3.5 Blanking and Latency
          4. 6.7.3.6.4 FCP Clocking
          5. 6.7.3.6.5 FCP Interrupts
          6. 6.7.3.6.6 FCP Programmer’s Guide
            1. 6.7.3.6.6.1 HWA Core Programming Details
            2. 6.7.3.6.6.2 HWA HTS Programming Details
            3. 6.7.3.6.6.3 HWA Data Transfer Programming Details
            4. 6.7.3.6.6.4 Initialization Sequence
            5. 6.7.3.6.6.5 Real-time Operating Requirements
            6. 6.7.3.6.6.6 Power Up/Down Sequence
        7. 6.7.3.7 VISS Edge Enhancer (EE)
          1. 6.7.3.7.1 Edge Enhancer Introduction
            1. 6.7.3.7.1.1 Edge Enhancer Filter
            2. 6.7.3.7.1.2 Edge Sharpener Filter
            3. 6.7.3.7.1.3 Merge Block
          2. 6.7.3.7.2 Edge Enhancer Programming Model
      4. 6.7.4 VPAC Lens Distortion Correction (LDC) Module
        1. 6.7.4.1 LDC Overview
          1. 6.7.4.1.1 LDC Features
        2. 6.7.4.2 LDC Functional Description
          1. 6.7.4.2.1  LDC Integration in VPAC
          2. 6.7.4.2.2  LDC Block Diagram
          3. 6.7.4.2.3  LDC Clocks
          4. 6.7.4.2.4  LDC Interrupts
            1. 6.7.4.2.4.1 LDC Interrupt Events Description
              1. 6.7.4.2.4.1.1 PIX_IBLK_OUTOFBOUND
              2. 6.7.4.2.4.1.2 MESH_IBLK_OUTOFBOUND
              3. 6.7.4.2.4.1.3 IFR_OUTOFBOUND
              4. 6.7.4.2.4.1.4 INT_SZOVF
              5. 6.7.4.2.4.1.5 VPAC_LDC_FR_DONE_EVT
              6. 6.7.4.2.4.1.6 VPAC_LDC_SL2_WR_ERR
              7. 6.7.4.2.4.1.7 PIX_IBLK_MEMOVF
              8. 6.7.4.2.4.1.8 MESH_IBLK_MEMOVF
              9. 6.7.4.2.4.1.9 VPAC_LDC_VBUSM_RD_ERR
          5. 6.7.4.2.5  LDC Affine Transform
          6. 6.7.4.2.6  LDC Perspective Transformation
          7. 6.7.4.2.7  LDC Lens Distortion Back Mapping
            1. 6.7.4.2.7.1 LDC Mesh Table Storage Format
          8. 6.7.4.2.8  LDC Pixel Interpolation
          9. 6.7.4.2.9  LDC Buffer Management
            1. 6.7.4.2.9.1 LDC Buffer Management
          10. 6.7.4.2.10 LDC Multi Region with Variable Block size
            1. 6.7.4.2.10.1 LDC Region Skip Feature
            2. 6.7.4.2.10.2 LDC Support for sub-set of 3x3 regions
            3. 6.7.4.2.10.3 LDC Limitations of Multi Region Scheme
            4. 6.7.4.2.10.4 LDC Multi Region Block Constrains
          11. 6.7.4.2.11 LDC Multi-pass Frame processing
          12. 6.7.4.2.12 LDC Input/Output Data Formats
          13. 6.7.4.2.13 LDC YUV422 to YUV420 Conversion
          14. 6.7.4.2.14 Independent Channel Control
          15. 6.7.4.2.15 LDC SL2 Interface (LSE)
            1. 6.7.4.2.15.1 LDC PSA (Parallel Signature Analysis)
          16. 6.7.4.2.16 LDC LUT Mapped Dual Output
          17. 6.7.4.2.17 LDC Band Width Controller
          18. 6.7.4.2.18 LDC Input Block Fetch Limit
          19. 6.7.4.2.19 LDC HTS Interface
          20. 6.7.4.2.20 LDC VBUSM Read Interface
          21. 6.7.4.2.21 Partial Input Frame Storage
          22. 6.7.4.2.22 Hybrid Addressing
        3. 6.7.4.3 LDC Programmers Guide
          1. 6.7.4.3.1 LDC Programming Geometric Distortion Mode
          2. 6.7.4.3.2 LDC Programming Rotational Video Stabilization (Affine Transformation)
          3. 6.7.4.3.3 LDC Programming Perspective Transformation
          4. 6.7.4.3.4 LDC Programming LSE
          5. 6.7.4.3.5 LDC Programming Restrictions and Special Cases
      5. 6.7.5 VPAC Multi-Scaler (MSC)
        1. 6.7.5.1 MSC Overview
          1. 6.7.5.1.1 MSC Features
        2. 6.7.5.2 MSC Functional Description
          1. 6.7.5.2.1 MSC Functional Overview
          2. 6.7.5.2.2 Resizer Algorithm Details
            1. 6.7.5.2.2.1 Multiple Scales Generations
            2. 6.7.5.2.2.2 Polyphase Filter
              1. 6.7.5.2.2.2.1 Interpolation/Resampling
              2. 6.7.5.2.2.2.2 Phase Calculation and Re-sampler
              3. 6.7.5.2.2.2.3 Shared Coefficient Buffers
              4. 6.7.5.2.2.2.4 Border Pixel Padding
            3. 6.7.5.2.2.3 ROI Handling
          3. 6.7.5.2.3 MSC Data Formats Supported
        3. 6.7.5.3 MSC Interrupt Conditions
          1. 6.7.5.3.1 CPU Interrupts
          2. 6.7.5.3.2 Interrupt Event Description
            1. 6.7.5.3.2.1 VPAC_MSC_LSE_FR_DONE_EVT_0/1 Events
            2. 6.7.5.3.2.2 VPAC_MSC_LSE_SL2_RD_ERR Interrupt Event
            3. 6.7.5.3.2.3 VPAC_MSC_LSE_SL2_WR_ERR Interrupt Event
        4. 6.7.5.4 MSC Submodule Details
          1. 6.7.5.4.1 MSC Configuration Interface (MSC_CFG)
          2. 6.7.5.4.2 MSC Load Store Engine (MSC_LSE)
            1. 6.7.5.4.2.1 MSC_LSE Overview
              1. 6.7.5.4.2.1.1 MSC_LSE Features
            2. 6.7.5.4.2.2 MSC_LSE Internal Data Loopback Channel
            3. 6.7.5.4.2.3 MSC_LSE PSA Support
            4. 6.7.5.4.2.4 MSC_LSE Feature Detailed Description
          3. 6.7.5.4.3 MSC_CORE (HWA Core)
            1. 6.7.5.4.3.1 MSC_CORE Overview
            2. 6.7.5.4.3.2 Polyphase Filter of Vertical/Horizontal Resizers
              1. 6.7.5.4.3.2.1 Filter Data Path Logic
              2. 6.7.5.4.3.2.2 Filter Phase Calculation
              3. 6.7.5.4.3.2.3 Filter Parameters
              4. 6.7.5.4.3.2.4 Single-Phase Filter Parameters
              5. 6.7.5.4.3.2.5 Interleaved Mode Handling
              6. 6.7.5.4.3.2.6 Input Skip Line Support
            3. 6.7.5.4.3.3 Scaler Filter Thread Mapping
            4. 6.7.5.4.3.4 Filter Coefficients
              1. 6.7.5.4.3.4.1 Filter Coefficient Selection Algorithm
              2. 6.7.5.4.3.4.2 Filter Coefficient Parameter Configuration
              3. 6.7.5.4.3.4.3 3/4/5-Tap Filter Configuration
            5. 6.7.5.4.3.5 Input/Output ROI Trimmers
        5. 6.7.5.5 MSC Performance
        6. 6.7.5.6 MSC Clocking
        7. 6.7.5.7 MSC Reset
        8. 6.7.5.8 MSC Programmer’s Guide
          1. 6.7.5.8.1 Programming Model
            1. 6.7.5.8.1.1 MSC Programming Guidelines
            2. 6.7.5.8.1.2 MSC_Core Programming Details
            3. 6.7.5.8.1.3 MSC_LSE Programming Details
              1. 6.7.5.8.1.3.1 Input Thread Configuration:
              2. 6.7.5.8.1.3.2 Output Channel Configuration
            4. 6.7.5.8.1.4 MSC HTS Programming Details
            5. 6.7.5.8.1.5 MSC Data Transfer Programming Details
            6. 6.7.5.8.1.6 LSE Interrupt Programming
          2. 6.7.5.8.2 Initialization Sequence
          3. 6.7.5.8.3 Real-Time Operating Requirements
          4. 6.7.5.8.4 Power Up/Down Sequence
      6. 6.7.6 VPAC Noise Filter (NF)
        1. 6.7.6.1 NF Overview
          1. 6.7.6.1.1 NF Supported Features
          2. 6.7.6.1.2 NF Not Supported Features
        2. 6.7.6.2 NF Functional Description
          1. 6.7.6.2.1 Functional Operation
            1. 6.7.6.2.1.1 Overview
            2. 6.7.6.2.1.2 NF Integration In VPAC
            3. 6.7.6.2.1.3 Algorithm Details
            4. 6.7.6.2.1.4 Data Format Support In VPAC
        3. 6.7.6.3 NF Interrupts
          1. 6.7.6.3.1 CPU Interrupts
          2. 6.7.6.3.2 Interrupt Event Description
            1. 6.7.6.3.2.1 NF_FRAME_DONE Event
            2. 6.7.6.3.2.2 NF_SL2_READ_ERROR Event
            3. 6.7.6.3.2.3 NF_SL2_WRITE_ERROR Event
        4. 6.7.6.4 NF Submodule Details
          1. 6.7.6.4.1 NF_CFG
            1. 6.7.6.4.1.1 VBUSP Configuration Interface
            2. 6.7.6.4.1.2 Configuration Register Address Map
          2. 6.7.6.4.2 NF_LSE
            1. 6.7.6.4.2.1 NF_LSE Overview
            2. 6.7.6.4.2.2 NF_LSE Feature Detailed Description
          3. 6.7.6.4.3 HTS Interface And Integration
            1. 6.7.6.4.3.1 Hardware Thread Scheduler (HTS)
            2. 6.7.6.4.3.2 Synchronization With HTS
          4. 6.7.6.4.4 Noise Filter Core Block Diagram
            1. 6.7.6.4.4.1 VP Port (NF_LSE To/From NF_CORE Over VBUSP Interface)
            2. 6.7.6.4.4.2 Space Weight Details
            3. 6.7.6.4.4.3 Weight Calculation Logic
              1. 6.7.6.4.4.3.1 Combined LUT For Space And Range Weights
            4. 6.7.6.4.4.4 Reciprocal Calculation Logic
            5. 6.7.6.4.4.5 Border Handling
              1. 6.7.6.4.4.5.1 Border Handling (Simple)
          5. 6.7.6.4.5 Usage As Generic 2D Filter Engine
          6. 6.7.6.4.6 Adaptive Bilateral Weight Support
          7. 6.7.6.4.7 Chroma Handling (Interleaved Mode)
        5. 6.7.6.5 NF Integration Details
          1. 6.7.6.5.1 Performance Requirements
          2. 6.7.6.5.2 Slave VBUSP Interface Clock
          3. 6.7.6.5.3 Clocking
        6. 6.7.6.6 NF Programmer’s Guide
          1. 6.7.6.6.1 Programming Model
            1. 6.7.6.6.1.1 HWA Core Programming Details
            2. 6.7.6.6.1.2 NF SL2 Wrapper Interface Programming Details
            3. 6.7.6.6.1.3 HWA HTS Programming Details
            4. 6.7.6.6.1.4 HWA Data Transfer Programming Details
          2. 6.7.6.6.2 Initialization Sequence
          3. 6.7.6.6.3 Real-Time Operating Requirements
          4. 6.7.6.6.4 Power Up/Down Sequence
          5. 6.7.6.6.5 Clock Stop
    8. 6.8 Depth and Motion Perception Accelerator (DMPAC)
      1. 6.8.1 DMPAC Overview
        1. 6.8.1.1 DMPAC Features
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
      2. 7.2.2 Spinlock Functional Description
        1. 7.2.2.1 Spinlock Software Reset
        2. 7.2.2.2 Spinlock Power Management
        3. 7.2.2.3 About Spinlocks
        4. 7.2.2.4 Spinlock Functional Operation
      3. 7.2.3 Spinlock Programming Guide
        1. 7.2.3.1 Spinlock Low-level Programming Models
          1. 7.2.3.1.1 Basic Spinlock Operations
            1. 7.2.3.1.1.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.3.1.1.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Functional Description
        1. 8.1.2.1  MSMC Block Diagram
        2. 8.1.2.2  MSMC On-Chip Memory Banking
        3. 8.1.2.3  MSMC Snoop Filter and Data Cache
          1. 8.1.2.3.1 Way Partitioning
          2. 8.1.2.3.2 Cache Size Configuration and Associativity
          3. 8.1.2.3.3 Write Back Invalidate
        4. 8.1.2.4  MSMC Access Protection Checks
        5. 8.1.2.5  MSMC Null Slave
        6. 8.1.2.6  MSMC Resource Arbitration
        7. 8.1.2.7  MSMC Error Detection and Correction
          1. 8.1.2.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.2.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.2.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.2.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.2.8  MSMC Interrupts
          1. 8.1.2.8.1 Raw Interrupt Registers
          2. 8.1.2.8.2 Interrupt Enable Registers
          3. 8.1.2.8.3 Triggered and Enabled Interrupts
        9. 8.1.2.9  MSMC Memory Regions
        10. 8.1.2.10 MSMC Hardware Coherence
          1. 8.1.2.10.1 Snoop Filter Broadcast Mode
        11. 8.1.2.11 MSMC Quality-of-Service
        12. 8.1.2.12 MSMC Memory Regions Protection
        13. 8.1.2.13 MSMC Cache Tag View
        14. 8.1.2.14 MSMC R50+ Features
          1. 8.1.2.14.1 Way Group Partitioning
            1. 8.1.2.14.1.1 MMRs Related to Way Group Partitioning Feature
              1. 8.1.2.14.1.1.1 RT_WAY_SELECT [Address = 0x8000]
              2. 8.1.2.14.1.1.2 NRT_WAY_SELECT [Address = 0x8008]
          2. 8.1.2.14.2 Write Back Invalidate
            1. 8.1.2.14.2.1 MMR Related to Snoop Filter Invalidate Feature
              1. 8.1.2.14.2.1.1 WBINV_CTRL [Address = 0x4000]
          3. 8.1.2.14.3 FFI Support
            1. 8.1.2.14.3.1 FFI Event Sequence
          4. 8.1.2.14.4 Broadcast Mode
          5. 8.1.2.14.5 DRU and SDMA Access Constraints (Access ARC Removal)
          6. 8.1.2.14.6 EMIF Interleaving
          7. 8.1.2.14.7 QoS Fix/RT Hazarding
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Functional Description
        1. 8.2.3.1 DDRSS MSMC2DDR Bridge
          1. 8.2.3.1.1 VBUSM.C Threads
          2. 8.2.3.1.2 Class of Service (CoS)
          3. 8.2.3.1.3 AXI Write Data All-Strobes
          4. 8.2.3.1.4 Inline ECC for SDRAM Data
            1. 8.2.3.1.4.1 ECC Cache
            2. 8.2.3.1.4.2 ECC Statistics
          5. 8.2.3.1.5 Opcode Checking
          6. 8.2.3.1.6 Address Alias Prevention
          7. 8.2.3.1.7 Data Error Detection and Correction
          8. 8.2.3.1.8 AXI Bus Timeout
        2. 8.2.3.2 DDRSS Interrupts
        3. 8.2.3.3 DDRSS Memory Regions
        4. 8.2.3.4 DDRSS ECC Support
        5. 8.2.3.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.3.6 DDR Controller Functional Description
          1. 8.2.3.6.1  DDR PHY Interface (DFI)
          2. 8.2.3.6.2  Command Queue
            1. 8.2.3.6.2.1 Placement Logic
            2. 8.2.3.6.2.2 Command Selection Logic
          3. 8.2.3.6.3  Low Power Control
          4. 8.2.3.6.4  Transaction Processing
          5. 8.2.3.6.5  BIST Engine
          6. 8.2.3.6.6  ECC Engine
          7. 8.2.3.6.7  Address Mapping
          8. 8.2.3.6.8  Paging Policy
          9. 8.2.3.6.9  DDR Controller Initialization
          10. 8.2.3.6.10 Programming LPDDR4 Memories
            1. 8.2.3.6.10.1 Frequency Set Point (FSP)
              1. 8.2.3.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.3.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.3.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.3.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.3.6.10.3 On-Die Termination
              1. 8.2.3.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.3.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.3.6.10.4 Byte Lane Swapping
            5. 8.2.3.6.10.5 DQS Interval Oscillator
              1. 8.2.3.6.10.5.1 Oscillator State Machine
            6. 8.2.3.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.3.6.10.6.1 Normal Operation
              2. 8.2.3.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.3.7 DDR PHY Functional Description
          1. 8.2.3.7.1  Data Slice
          2. 8.2.3.7.2  Address Slice
            1. 8.2.3.7.2.1 Address Swapping
          3. 8.2.3.7.3  Address/Control Slice
          4. 8.2.3.7.4  Clock Slice
          5. 8.2.3.7.5  DDR PHY Initialization
          6. 8.2.3.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.3.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.3.7.8  Low-Power Modes
          9. 8.2.3.7.9  Training Support
            1. 8.2.3.7.9.1 Write Leveling
            2. 8.2.3.7.9.2 Read Gate Training
            3. 8.2.3.7.9.3 Read Data Eye Training
            4. 8.2.3.7.9.4 Write DQ Training
            5. 8.2.3.7.9.5 CA Training
            6. 8.2.3.7.9.6 CS Training
          10. 8.2.3.7.10 Data Bus Inversion (DBI)
          11. 8.2.3.7.11 I/O Pad Calibration
          12. 8.2.3.7.12 DQS Error
        8. 8.2.3.8 PI Functional Description
          1. 8.2.3.8.1 PI Initialization
      4. 8.2.4 DDRSS Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
      2. 8.3.2 PVU Functional Description
        1. 8.3.2.1  Functional Operation Overview
        2. 8.3.2.2  PVU Channels
        3. 8.3.2.3  TLB
        4. 8.3.2.4  TLB Entry
        5. 8.3.2.5  TLB Selection
        6. 8.3.2.6  DMA Classes
        7. 8.3.2.7  General virtIDs
        8. 8.3.2.8  TLB Lookup
        9. 8.3.2.9  TLB Miss
        10. 8.3.2.10 Multiple Matching Entries
        11. 8.3.2.11 TLB Disable
        12. 8.3.2.12 TLB Chaining
        13. 8.3.2.13 TLB Permissions
        14. 8.3.2.14 Translation
        15. 8.3.2.15 Memory Attributes
        16. 8.3.2.16 Faulted Transactions
        17. 8.3.2.17 Non-Virtual Transactions
        18. 8.3.2.18 Allowed virtIDs
        19. 8.3.2.19 Software Control
        20. 8.3.2.20 Fault Logging
        21. 8.3.2.21 Alignment Restrictions
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Functional Description
          1. 9.2.1.2.1 Arm GIC-500
          2. 9.2.1.2.2 GIC Interrupt Types
          3. 9.2.1.2.3 GIC Interfaces
          4. 9.2.1.2.4 GIC Interrupt Outputs
          5. 9.2.1.2.5 GIC ECC Support
          6. 9.2.1.2.6 GIC AXI2VBUSM and VBUSM2AXI Bridges
      2. 9.2.2 Cluster Level Event Controller (CLEC)
        1. 9.2.2.1 CLEC Overview
        2. 9.2.2.2 CLEC Functional Description
          1. 9.2.2.2.1 CLEC Interrupt Event Routing
          2. 9.2.2.2.2 CLEC Virtualization, Isolation and Access Control
          3. 9.2.2.2.3 CLEC Memory Protection
          4. 9.2.2.2.4 CLEC ECC Support
          5. 9.2.2.2.5 CLEC Intra-Core Communication
          6. 9.2.2.2.6 CLEC Event Maps
            1. 9.2.2.2.6.1 CLEC ESM Event Routing
      3. 9.2.3 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Registers
        1. 9.3.2.1 CMPEVENT_INTRTR Registers
        2. 9.3.2.2 GPIOMUX_INTRTR Registers
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR Registers
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR Registers
        5. 9.3.2.5 TIMESYNC_INTRTR Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1  CMPEVENT_INTRTR0_INTERRUPT_MAP
      2. 9.4.2  COMPUTE_CLUSTERHP0_CLEC_0_INTERRUPT_MAP
      3. 9.4.3  COMPUTE_CLUSTERHP0_GIC500SS_0_INTERRUPT_MAP
      4. 9.4.4  CPSW_9XUSSM0_INTERRUPT_MAP
      5. 9.4.5  CPSW1_COMMON_0_INTERRUPT_MAP
      6. 9.4.6  CPSW1_INTERRUPT_MAP
      7. 9.4.7  DMPAC0_INTD_0_INTERRUPT_MAP
      8. 9.4.8  ESM0_INTERRUPT_MAP
      9. 9.4.9  GLUELOGIC_A72_IPC_INTR_GLUE_INTERRUPT_MAP
      10. 9.4.10 GLUELOGIC_DBG_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      11. 9.4.11 GLUELOGIC_FW_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      12. 9.4.12 GLUELOGIC_GPU_GPIO_INT_GLUE_INTERRUPT_MAP
      13. 9.4.13 GLUELOGIC_MAIN_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      14. 9.4.14 GLUELOGIC_NONFW_CBASS_INTR_OR_GLUE_INTERRUPT_MAP
      15. 9.4.15 GPIOMUX_INTRTR0_INTERRUPT_MAP
      16. 9.4.16 MAIN_GPIO0_VIRT_INTERRUPT_MAP
      17. 9.4.17 MAIN2MCU_LVL_INTRTR0_INTERRUPT_MAP
      18. 9.4.18 MAIN2MCU_PLS_INTRTR0_INTERRUPT_MAP
      19. 9.4.19 MCU_ADC12FCC0_COMMON_0_INTERRUPT_MAP
      20. 9.4.20 MCU_ADC12FCC1_COMMON_0_INTERRUPT_MAP
      21. 9.4.21 MCU_CPSW0_COMMON_0_INTERRUPT_MAP
      22. 9.4.22 MCU_CPSW0_INTERRUPT_MAP
      23. 9.4.23 MCU_ESM0_INTERRUPT_MAP
      24. 9.4.24 MCU_NAVSS0_INTR_ROUTER_0_INTERRUPT_MAP
      25. 9.4.25 MCU_NAVSS0_UDMASS_INTA_0_INTERRUPT_MAP
      26. 9.4.26 MCU_PDMA0_INTERRUPT_MAP
      27. 9.4.27 MCU_PDMA1_INTERRUPT_MAP
      28. 9.4.28 MCU_PDMA2_INTERRUPT_MAP
      29. 9.4.29 MCU_PDMA3_INTERRUPT_MAP
      30. 9.4.30 MCU_R5FSS0_CORE0_INTERRUPT_MAP
      31. 9.4.31 MCU_R5FSS0_CORE1_INTERRUPT_MAP
      32. 9.4.32 NAVSS0_INTERRUPT_MAP
      33. 9.4.33 NAVSS0_INTR_0_INTERRUPT_MAP
      34. 9.4.34 NAVSS0_UDMASS_INTA_0_INTERRUPT_MAP
      35. 9.4.35 PCIE0_INTERRUPT_MAP
      36. 9.4.36 PCIE1_INTERRUPT_MAP
      37. 9.4.37 PCIE2_INTERRUPT_MAP
      38. 9.4.38 PCIE3_INTERRUPT_MAP
      39. 9.4.39 PDMA0_INTERRUPT_MAP
      40. 9.4.40 PDMA1_INTERRUPT_MAP
      41. 9.4.41 PDMA2_INTERRUPT_MAP
      42. 9.4.42 PDMA3_INTERRUPT_MAP
      43. 9.4.43 PDMA4_INTERRUPT_MAP
      44. 9.4.44 PDMA5_COMMON_0_INTERRUPT_MAP
      45. 9.4.45 PDMA6_COMMON_0_INTERRUPT_MAP
      46. 9.4.46 PDMA7_COMMON_0_INTERRUPT_MAP
      47. 9.4.47 PDMA8_INTERRUPT_MAP
      48. 9.4.48 PINFUNCTION_SYNC0_OUTOUT_INTERRUPT_MAP
      49. 9.4.49 PINFUNCTION_SYNC1_OUTOUT_INTERRUPT_MAP
      50. 9.4.50 PINFUNCTION_SYNC2_OUTOUT_INTERRUPT_MAP
      51. 9.4.51 PINFUNCTION_SYNC3_OUTOUT_INTERRUPT_MAP
      52. 9.4.52 R5FSS0_CORE0_INTERRUPT_MAP
      53. 9.4.53 R5FSS0_CORE1_INTERRUPT_MAP
      54. 9.4.54 R5FSS1_CORE0_INTERRUPT_MAP
      55. 9.4.55 R5FSS1_CORE1_INTERRUPT_MAP
      56. 9.4.56 R5FSS2_CORE0_INTERRUPT_MAP
      57. 9.4.57 R5FSS2_CORE1_INTERRUPT_MAP
      58. 9.4.58 TIMESYNC_INTRTR0_INTERRUPT_MAP
      59. 9.4.59 VUSR_DUAL0_INTERRUPT_MAP
      60. 9.4.60 WKUP_ESM0_INTERRUPT_MAP
      61. 9.4.61 WKUP_GPIO_VIRT_INTERRUPT_MAP
      62. 9.4.62 WKUP_GPIOMUX_INTRTR0_INTERRUPT_MAP
      63. 9.4.63 WKUP_HSM0_INTERRUPT_MAP
      64. 9.4.64 WKUP_SMS0_COMMON_0_INTERRUPT_MAP
      65. 9.4.65 WKUP_TIFS0_INTERRUPT_MAP
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA-P Transmit Channel Pause
        6. 10.1.3.6  UDMA-P Transmit Operation (Host Packet Type)
        7. 10.1.3.7  UDMA-P Transmit Operation (Monolithic Packet)
        8. 10.1.3.8  UDMA Transmit Operation (TR Packet)
        9. 10.1.3.9  UDMA Transmit Operation (Direct TR)
        10. 10.1.3.10 UDMA Transmit Error/Exception Handling
          1. 10.1.3.10.1 Null Icnt0 Error
          2. 10.1.3.10.2 Unsupported TR Type
          3. 10.1.3.10.3 Bus Errors
        11. 10.1.3.11 UDMA Receive Channel Setup (All Packet Types)
        12. 10.1.3.12 UDMA Receive Channel Teardown
        13. 10.1.3.13 UDMA-P Receive Channel Pause
        14. 10.1.3.14 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        15. 10.1.3.15 UDMA-P Receive FlowID Firewall Operation
        16. 10.1.3.16 UDMA-P Receive Operation (Host Packet)
        17. 10.1.3.17 UDMA-P Receive Operation (Monolithic Packet)
        18. 10.1.3.18 UDMA Receive Operation (TR Packet)
        19. 10.1.3.19 UDMA Receive Operation (Direct TR)
        20. 10.1.3.20 UDMA Receive Error/Exception Handling
          1. 10.1.3.20.1 Error Conditions
            1. 10.1.3.20.1.1 Bus Errors
            2. 10.1.3.20.1.2 Null Icnt0 Error
            3. 10.1.3.20.1.3 Unsupported TR Type
          2. 10.1.3.20.2 Exception Conditions Exception Conditions
            1. 10.1.3.20.2.1 Descriptor Starvation
            2. 10.1.3.20.2.2 Protocol Errors
            3. 10.1.3.20.2.3 Dropped Packets
            4. 10.1.3.20.2.4 Reception of EOL Delimiter
            5. 10.1.3.20.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.20.2.6 EOP Asserted Late (Long Packets)
        21. 10.1.3.21 UTC Operation
        22. 10.1.3.22 UTC Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Handling
            1. 10.1.3.22.1.1 Null Icnt0 Error
            2. 10.1.3.22.1.2 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions
            1. 10.1.3.22.2.1 Reception of EOL Delimiter
            2. 10.1.3.22.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.22.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1 Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Functional Description
        3. 10.2.1.3 NAVSS Interrupt Configuration
          1. 10.2.1.3.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.3.1.1 NAVSS Interrupts Description
            2. 10.2.1.3.1.2 Application Example
      2. 10.2.2 MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Functional Description
      3. 10.2.3 Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Functional Description
          1. 10.2.3.2.1 Block Diagram
          2. 10.2.3.2.2 General Functionality
            1. 10.2.3.2.2.1  Operational States
            2. 10.2.3.2.2.2  Tx Channel Allocation
            3. 10.2.3.2.2.3  Rx Channel Allocation
            4. 10.2.3.2.2.4  Tx Teardown
            5. 10.2.3.2.2.5  Rx Teardown
            6. 10.2.3.2.2.6  Tx Clock Stop
            7. 10.2.3.2.2.7  Rx Clock Stop
            8. 10.2.3.2.2.8  Rx Thread Enables
            9. 10.2.3.2.2.9  Events
              1. 10.2.3.2.2.9.1 Local Event Inputs
              2. 10.2.3.2.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.2.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.2.2.10 Emulation Control
          3. 10.2.3.2.3 Packet Oriented Transmit Operation
            1. 10.2.3.2.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.2.4 Packet Oriented Receive Operation
            1. 10.2.3.2.4.1 Rx Packet Drop
            2. 10.2.3.2.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.2.5 Third Party Mode Operation
            1. 10.2.3.2.5.1 Events and Flow Control
              1. 10.2.3.2.5.1.1 Channel Triggering
              2. 10.2.3.2.5.1.2 Internal TR Completion Events
            2. 10.2.3.2.5.2 Transmit Operation
              1. 10.2.3.2.5.2.1 Transfer Request
              2. 10.2.3.2.5.2.2 Transfer Response
              3. 10.2.3.2.5.2.3 Data Transfer
              4. 10.2.3.2.5.2.4 Memory Interface Transactions
              5. 10.2.3.2.5.2.5 Error Handling
            3. 10.2.3.2.5.3 Receive Operation
              1. 10.2.3.2.5.3.1 Transfer Request
              2. 10.2.3.2.5.3.2 Transfer Response
              3. 10.2.3.2.5.3.3 Error Handling
            4. 10.2.3.2.5.4 Data Transfer
              1. 10.2.3.2.5.4.1 Memory Interface Transactions
              2. 10.2.3.2.5.4.2 Rx Packet Drop
      4. 10.2.4 Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Parameters
        2. 10.2.4.2 RINGACC Functional Description
          1. 10.2.4.2.1 Block Diagram
            1. 10.2.4.2.1.1  Configuration Registers
            2. 10.2.4.2.1.2  Source Command FIFO
            3. 10.2.4.2.1.3  Source Write Data FIFO
            4. 10.2.4.2.1.4  Source Read Data FIFO
            5. 10.2.4.2.1.5  Source Write Status FIFO
            6. 10.2.4.2.1.6  Main State Machine
            7. 10.2.4.2.1.7  Destination Command FIFO
            8. 10.2.4.2.1.8  Destination Write Data FIFO
            9. 10.2.4.2.1.9  Destination Read Data FIFO
            10. 10.2.4.2.1.10 Destination Write Status FIFO
          2. 10.2.4.2.2 RINGACC Functional Operation
            1. 10.2.4.2.2.1 Queue Modes
              1. 10.2.4.2.2.1.1 Ring Mode
              2. 10.2.4.2.2.1.2 Messaging Mode
              3. 10.2.4.2.2.1.3 Credentials Mode
              4. 10.2.4.2.2.1.4 Queue Manager Mode
              5. 10.2.4.2.2.1.5 Peek Support
              6. 10.2.4.2.2.1.6 Index Register Operation
            2. 10.2.4.2.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.2.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.2.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.2.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.2.2.6 Host Doorbell Access
            7. 10.2.4.2.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.2.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.2.2.9 Mismatched Element Size Handling
          3. 10.2.4.2.3 Events
          4. 10.2.4.2.4 Bus Error Handling
          5. 10.2.4.2.5 Monitors
            1. 10.2.4.2.5.1 Threshold Monitor
            2. 10.2.4.2.5.2 Watermark Monitor
            3. 10.2.4.2.5.3 Starvation Monitor
            4. 10.2.4.2.5.4 Statistics Monitor
            5. 10.2.4.2.5.5 Overflow
            6. 10.2.4.2.5.6 Ring Update Port
            7. 10.2.4.2.5.7 Tracing
      5. 10.2.5 Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
        2. 10.2.5.2 Proxy Functional Description
          1. 10.2.5.2.1  Targets
            1. 10.2.5.2.1.1 Ring Accelerator
          2. 10.2.5.2.2  Proxy Sizes
          3. 10.2.5.2.3  Proxy Interleaving
          4. 10.2.5.2.4  Proxy Host States
          5. 10.2.5.2.5  Proxy Host Channel Selection
          6. 10.2.5.2.6  Proxy Host Access
            1. 10.2.5.2.6.1 Proxy Host Writes
            2. 10.2.5.2.6.2 Proxy Host Reads
          7. 10.2.5.2.7  Permission Inheritance
          8. 10.2.5.2.8  Buffer Size
          9. 10.2.5.2.9  Error Events
          10. 10.2.5.2.10 Debug Reads
      6. 10.2.6 Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
        2. 10.2.6.2 Secure Proxy Functional Description
          1. 10.2.6.2.1  Targets
            1. 10.2.6.2.1.1 Ring Accelerator
          2. 10.2.6.2.2  Buffers
            1. 10.2.6.2.2.1 Proxy Credits
            2. 10.2.6.2.2.2 Proxy Private Word
            3. 10.2.6.2.2.3 Completion Byte
          3. 10.2.6.2.3  Proxy Thread Sizes
          4. 10.2.6.2.4  Proxy Thread Interleaving
          5. 10.2.6.2.5  Proxy States
          6. 10.2.6.2.6  Proxy Host Access
            1. 10.2.6.2.6.1 Proxy Host Writes
            2. 10.2.6.2.6.2 Proxy Host Reads
            3. 10.2.6.2.6.3 Buffer Accesses
            4. 10.2.6.2.6.4 Target Access
            5. 10.2.6.2.6.5 Error State
          7. 10.2.6.2.7  Permission Inheritance
          8. 10.2.6.2.8  Resource Association
          9. 10.2.6.2.9  Direction
          10. 10.2.6.2.10 Threshold Events
          11. 10.2.6.2.11 Error Events
          12. 10.2.6.2.12 Bus Errors and Credits
          13. 10.2.6.2.13 Debug
      7. 10.2.7 Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Functional Description
          1. 10.2.7.2.1 Submodule Descriptions
            1. 10.2.7.2.1.1 Status/Mask Registers
            2. 10.2.7.2.1.2 Interrupt Mapping Block
            3. 10.2.7.2.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.2.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.2.1.5 Global Event Multicast
          2. 10.2.7.2.2 General Functionality
            1. 10.2.7.2.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.2.2.2 Interrupt Status
            3. 10.2.7.2.2.3 Interrupt Masked Status
            4. 10.2.7.2.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.2.2.5 Interrupt Output Generation
            6. 10.2.7.2.2.6 Global Event Counting
            7. 10.2.7.2.2.7 Local Event to Global Event Conversion
            8. 10.2.7.2.2.8 Global Event Multicast
      8. 10.2.8 Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
      9. 10.2.9 NAVSS North Bridge (NB)
        1. 10.2.9.1 NB Overview
          1. 10.2.9.1.1 Features Supported
          2. 10.2.9.1.2 NB Parameters
            1. 10.2.9.1.2.1 Compliance to Standards
            2. 10.2.9.1.2.2 Features Not Supported
        2. 10.2.9.2 NB Functional Description
          1. 10.2.9.2.1  VBUSM Slave Interfaces
          2. 10.2.9.2.2  VBUSM Master Interface
          3. 10.2.9.2.3  VBUSM.C Interfaces
            1. 10.2.9.2.3.1 Multi-Threading
            2. 10.2.9.2.3.2 Write Command Crediting
            3. 10.2.9.2.3.3 Early Credit Response
            4. 10.2.9.2.3.4 Priority Escalation
          4. 10.2.9.2.4  Source M2M Bridges
          5. 10.2.9.2.5  Destination M2M Bridge
          6. 10.2.9.2.6  M2C Bridge
          7. 10.2.9.2.7  Memory Attribute Tables
          8. 10.2.9.2.8  Outstanding Read Data Limiter
          9. 10.2.9.2.9  Ordering
          10. 10.2.9.2.10 Quality of Service
          11. 10.2.9.2.11 IDLE Behavior
          12. 10.2.9.2.12 Clock Power Management
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA5 (PDMA_MCAN) Features
            6. 10.3.1.1.1.6  PDMA6 (PDMA_MCASP_G0) Features
            7. 10.3.1.1.1.7  PDMA9 (PDMA_SPI_G0) Features
            8. 10.3.1.1.1.8  PDMA10 (PDMA_SPI_G1) Features
            9. 10.3.1.1.1.9  PDMA13 (PDMA_USART_G0) Features
            10. 10.3.1.1.1.10 PDMA14 (PDMA_USART_G1) Features
            11. 10.3.1.1.1.11 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Functional Description
          1. 10.3.1.2.1 PDMA Functional Blocks
            1. 10.3.1.2.1.1 Scheduler
            2. 10.3.1.2.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.2.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.2.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.2.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.2.2 PDMA General Functionality
            1. 10.3.1.2.2.1 Operational States
            2. 10.3.1.2.2.2 Clock Stop
            3. 10.3.1.2.2.3 Emulation Control
          3. 10.3.1.2.3 PDMA Events and Flow Control
            1. 10.3.1.2.3.1 Channel Types
              1. 10.3.1.2.3.1.1 X-Y FIFO Mode
              2. 10.3.1.2.3.1.2 MCAN Mode
              3. 10.3.1.2.3.1.3 AASRC Mode
            2. 10.3.1.2.3.2 Channel Triggering
            3. 10.3.1.2.3.3 Completion Events
          4. 10.3.1.2.4 PDMA Transmit Operation
            1. 10.3.1.2.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.2.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.2.4.3 Destination Channel Initialization
              1. 10.3.1.2.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.2.4.3.2 Static Transfer Request Setup
              3. 10.3.1.2.4.3.3 PSI-L Destination Thread Enables
            4. 10.3.1.2.4.4 Data Transfer
              1. 10.3.1.2.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.2.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.2.4.4.2 MCAN Mode Channel
                1. 10.3.1.2.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.2.4.4.3 AASRC Mode Channel
            5. 10.3.1.2.4.5 Tx Pause
            6. 10.3.1.2.4.6 Tx Teardown
            7. 10.3.1.2.4.7 Tx Channel Reset
            8. 10.3.1.2.4.8 Tx Debug/State Registers
          5. 10.3.1.2.5 PDMA Receive Operation
            1. 10.3.1.2.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.2.5.2 Source Channel Initialization
              1. 10.3.1.2.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.2.5.2.2 Static Transfer Request Setup
              3. 10.3.1.2.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.2.5.3 Data Transfer
              1. 10.3.1.2.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.2.5.3.2 MCAN Mode Channel
                1. 10.3.1.2.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.2.5.3.3 AASRC Mode Channel
            4. 10.3.1.2.5.4 Rx Pause
            5. 10.3.1.2.5.5 Rx Teardown
            6. 10.3.1.2.5.6 Rx Channel Reset
            7. 10.3.1.2.5.7 Rx Debug/State Register
          6. 10.3.1.2.6 PDMA ECC Support
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_MCAN Event Map
          2. 10.3.2.2.2 PDMA_MCASP_G0 Event Map
          3. 10.3.2.2.3 PDMA_SPI_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G1 Event Map
          5. 10.3.2.2.5 PDMA_USART_G0 Event Map
          6. 10.3.2.2.6 PDMA_USART_G1 Event Map
          7. 10.3.2.2.7 PDMA_USART_G2 Event Map
    4. 10.4 Data Routing Unit (DRU)
      1. 10.4.1 DRU Overview
      2. 10.4.2 DRU Integration
      3. 10.4.3 DRU Functional Description
        1. 10.4.3.1 DRU Basic Functionality
          1. 10.4.3.1.1 Queues
          2. 10.4.3.1.2 Channel Configuration
            1. 10.4.3.1.2.1 Non-realtime Channel Configuration
            2. 10.4.3.1.2.2 Realtime Channel Configuration
          3. 10.4.3.1.3 TR Submission
            1. 10.4.3.1.3.1 Direct TR Submission
            2. 10.4.3.1.3.2 PSI-L TR Submission
          4. 10.4.3.1.4 TR Removal from Channel
          5. 10.4.3.1.5 Channel Tear Down
            1. 10.4.3.1.5.1 Tear Down Completion
        2. 10.4.3.2 DRU Virtualization
        3. 10.4.3.3 DRU Compression and Decompression
        4. 10.4.3.4 DRU Output Events
        5. 10.4.3.5 DRU Address Fetch Algorithm, TR and CR Formats
          1. 10.4.3.5.1 Transpose
          2. 10.4.3.5.2 Circular Buffering
        6. 10.4.3.6 DRU Firewalls
        7. 10.4.3.7 DRU Errors
        8. 10.4.3.8 DRU Configurations
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
      2. 11.1.2 CPTS Functional Description
        1. 11.1.2.1  CPTS Architecture
        2. 11.1.2.2  CPTS Initialization
        3. 11.1.2.3  32-bit Time Stamp Value
        4. 11.1.2.4  64-bit Time Stamp Value
          1. 11.1.2.4.1 64-Bit Timestamp Nudge
          2. 11.1.2.4.2 64-bit Timestamp PPM
        5. 11.1.2.5  Event FIFO
        6. 11.1.2.6  Timestamp Compare Output
          1. 11.1.2.6.1 Non-Toggle Mode
          2. 11.1.2.6.2 Toggle Mode
        7. 11.1.2.7  Timestamp Sync Output
        8. 11.1.2.8  Timestamp GENF Output
          1. 11.1.2.8.1 GENFn Nudge
          2. 11.1.2.8.2 GENFn PPM
        9. 11.1.2.9  Time Sync Events
          1. 11.1.2.9.1 Time Stamp Push Event
          2. 11.1.2.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.2.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.2.9.4 Hardware Time Stamp Push Event
        10. 11.1.2.10 Timestamp Compare Event
        11. 11.1.2.11 CPTS Interrupt Handling
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
      2. 11.2.2 Timer Manager Functional Description
        1. 11.2.2.1 Timer Manager Function Overview
        2. 11.2.2.2 Timer Counter
          1. 11.2.2.2.1 Timer Counter Rollover
        3. 11.2.2.3 Timer Control Module (FSM)
        4. 11.2.2.4 Timer Reprogramming
        5. 11.2.2.5 Event FIFO
        6. 11.2.2.6 Output Event Lookup (OES RAM)
      3. 11.2.3 Timer Manager Programming Guide
        1. 11.2.3.1 Timer Manager Low-level Programming Models
          1. 11.2.3.1.1 Initialization Sequence
          2. 11.2.3.1.2 Real-time Operating Requirements
            1. 11.2.3.1.2.1 Timer Touch
            2. 11.2.3.1.2.2 Timer Disable
            3. 11.2.3.1.2.3 Timer Enable
          3. 11.2.3.1.3 Power Up/Power Down Sequence
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
      3. 11.3.3 Time Sync Event Sources
  14. 12Peripherals
    1. 12.1  General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Ports
        2. 12.1.1.2 ADC Environment
        3. 12.1.1.3 ADC Functional Description
          1. 12.1.1.3.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.3.1.1 Step Enable
            2. 12.1.1.3.1.2 Step Configuration
              1. 12.1.1.3.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.3.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.3.1.2.3 Averaging of Samples
              4. 12.1.1.3.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.3.1.2.5 Differential Control
              6. 12.1.1.3.1.2.6 FIFO Select
              7. 12.1.1.3.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.3.1.3 Open Delay and Sample Delay
              1. 12.1.1.3.1.3.1 Open Delay
              2. 12.1.1.3.1.3.2 Sample Delay
            4. 12.1.1.3.1.4 Interrupts
            5. 12.1.1.3.1.5 Power Management
            6. 12.1.1.3.1.6 DMA Requests
          2. 12.1.1.3.2 ADC AFE Functional Description
            1. 12.1.1.3.2.1 AFE Functional Block Diagram
          3. 12.1.1.3.3 ADC FIFOs and DMA
            1. 12.1.1.3.3.1 FIFOs
            2. 12.1.1.3.3.2 DMA
          4. 12.1.1.3.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.3.4.1 Testing ECC Error Injection
          5. 12.1.1.3.5 ADC Functional Debug Mode
        4. 12.1.1.4 ADC Programming Guide
          1. 12.1.1.4.1 ADC Low-Level Programming Models
            1. 12.1.1.4.1.1 During Operation
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Ports
        2. 12.1.2.2 GPIO Environment
        3. 12.1.2.3 GPIO Functional Description
          1. 12.1.2.3.1 GPIO Block Diagram
          2. 12.1.2.3.2 GPIO Function
          3. 12.1.2.3.3 GPIO Interrupt and Event Generation
            1. 12.1.2.3.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.3.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.3.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.3.4 GPIO Emulation Halt Operation
        4. 12.1.2.4 GPIO Programming Guide
          1. 12.1.2.4.1 GPIO Low-Level Programming Models
            1. 12.1.2.4.1.1 GPIO Operational Modes Configuration
              1. 12.1.2.4.1.1.1 GPIO Read Input Register
              2. 12.1.2.4.1.1.2 GPIO Set Bit Function
              3. 12.1.2.4.1.1.3 GPIO Clear Bit Function
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Ports
        2. 12.1.3.2 I2C Environment
        3. 12.1.3.3 I2C Functional Description
          1. 12.1.3.3.1 I2C Block Diagram
          2. 12.1.3.3.2 I2C Clocks
            1. 12.1.3.3.2.1 I2C Clocking
            2. 12.1.3.3.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.3.3 I2C Software Reset
          4. 12.1.3.3.4 I2C Power Management
          5. 12.1.3.3.5 I2C Interrupt Requests
          6. 12.1.3.3.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.3.7 I2C FIFO Management
            1. 12.1.3.3.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.3.7.2 I2C FIFO Polling Mode
            3. 12.1.3.3.7.3 I2C Draining Feature
          8. 12.1.3.3.8 I2C Noise Filter
          9. 12.1.3.3.9 I2C System Test Mode
        4. 12.1.3.4 I2C Programming Guide
          1. 12.1.3.4.1 I2C Low-Level Programming Models
            1. 12.1.3.4.1.1 I2C Programming Model
              1. 12.1.3.4.1.1.1 Main Program
                1. 12.1.3.4.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.4.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.4.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.4.1.1.1.4 Initiate a Transfer
                5. 12.1.3.4.1.1.1.5 Receive Data
                6. 12.1.3.4.1.1.1.6 Transmit Data
              2. 12.1.3.4.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.4.1.1.3 Programming Flow-Diagrams
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Ports
        2. 12.1.4.2 I3C Environment
        3. 12.1.4.3 I3C Functional Description
          1. 12.1.4.3.1  I3C Block Diagram
          2. 12.1.4.3.2  I3C Clock Configuration
            1. 12.1.4.3.2.1 Setting Base Frequencies
            2. 12.1.4.3.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.3.2.3 Open-Drain SCL Timing
            4. 12.1.4.3.2.4 Changing Programmed Frequencies
          3. 12.1.4.3.3  I3C Interrupt Requests
          4. 12.1.4.3.4  I3C Power Configuration
          5. 12.1.4.3.5  I3C Dynamic Address Management
          6. 12.1.4.3.6  I3C Retaining Registers Space
          7. 12.1.4.3.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.3.8  I3C Sending CCC Messages
          9. 12.1.4.3.9  I3C In-Band Interrupt
            1. 12.1.4.3.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.3.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.3.10 I3C Hot-Join Request
          11. 12.1.4.3.11 I3C Immediate Commands
          12. 12.1.4.3.12 I3C Host Commands
          13. 12.1.4.3.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.3.13.1 SDR Private Write Message
            2. 12.1.4.3.13.2 SDR Private Read Message
            3. 12.1.4.3.13.3 SDR Payload Length Adjustment
        4. 12.1.4.4 I3C Programming Guide
          1. 12.1.4.4.1 I3C Power-On Programming Model
          2. 12.1.4.4.2 I3C Static Devices Programming
          3. 12.1.4.4.3 I3C DAA Procedure Initiation
          4. 12.1.4.4.4 I3C SDR Write Message Programming Model
          5. 12.1.4.4.5 I3C SDR Read Message Programming Model
          6. 12.1.4.4.6 I3C DDR Write Message Programming Model
          7. 12.1.4.4.7 I3C DDR Read Message Programming Model
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Ports
        2. 12.1.5.2 MCSPI Environment
        3. 12.1.5.3 MCSPI Functional Description
          1. 12.1.5.3.1 SPI Block Diagram
          2. 12.1.5.3.2 MCSPI Reset
          3. 12.1.5.3.3 MCSPI Controller Mode
            1. 12.1.5.3.3.1 Controller Mode Features
            2. 12.1.5.3.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.3.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.3.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.3.3.5 Single-Channel Controller Mode
              1. 12.1.5.3.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.3.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.3.3.5.3 Turbo Mode
            6. 12.1.5.3.3.6 Start-Bit Mode
            7. 12.1.5.3.3.7 Chip-Select Timing Control
            8. 12.1.5.3.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.3.3.8.1 Clock Ratio Granularity
          4. 12.1.5.3.4 MCSPI Peripheral Mode
            1. 12.1.5.3.4.1 Dedicated Resources
            2. 12.1.5.3.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.3.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.3.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.3.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.3.6 MCSPI FIFO Buffer Management
            1. 12.1.5.3.6.1 Buffer Almost Full
            2. 12.1.5.3.6.2 Buffer Almost Empty
            3. 12.1.5.3.6.3 End of Transfer Management
            4. 12.1.5.3.6.4 Multiple MCSPI Word Access
            5. 12.1.5.3.6.5 First MCSPI Word Delay
          7. 12.1.5.3.7 MCSPI Interrupts
            1. 12.1.5.3.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.3.7.1.1 TXx_EMPTY
              2. 12.1.5.3.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.3.7.1.3 RXx_ FULL
              4. 12.1.5.3.7.1.4 End Of Word Count
            2. 12.1.5.3.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.3.7.2.1 TXx_EMPTY
              2. 12.1.5.3.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.3.7.2.3 RXx_FULL
              4. 12.1.5.3.7.2.4 RX0_OVERFLOW
              5. 12.1.5.3.7.2.5 End Of Word Count
            3. 12.1.5.3.7.3 Interrupt-Driven Operation
            4. 12.1.5.3.7.4 Polling
          8. 12.1.5.3.8 MCSPI DMA Requests
          9. 12.1.5.3.9 MCSPI Power Saving Management
            1. 12.1.5.3.9.1 Normal Mode
            2. 12.1.5.3.9.2 Idle Mode
              1. 12.1.5.3.9.2.1 Force-Idle Mode
        4. 12.1.5.4 MCSPI Programming Guide
          1. 12.1.5.4.1 MCSPI Operational Mode Configuration
            1. 12.1.5.4.1.1 MCSPI Operational Modes
              1. 12.1.5.4.1.1.1 Common Transfer Sequence
              2. 12.1.5.4.1.1.2 End of Transfer Sequences
              3. 12.1.5.4.1.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.4.1.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.4.1.1.4.1 Based on Interrupt Requests
                2. 12.1.5.4.1.1.4.2 Based on DMA Write Requests
              5. 12.1.5.4.1.1.5 Controller Normal Receive-Only
                1. 12.1.5.4.1.1.5.1 Based on Interrupt Requests
                2. 12.1.5.4.1.1.5.2 Based on DMA Read Requests
              6. 12.1.5.4.1.1.6 Controller Turbo Receive-Only
                1. 12.1.5.4.1.1.6.1 Based on Interrupt Requests
                2. 12.1.5.4.1.1.6.2 Based on DMA Read Requests
              7. 12.1.5.4.1.1.7 Peripheral Receive-Only
              8. 12.1.5.4.1.1.8 Transfer Procedures With FIFO
                1. 12.1.5.4.1.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.4.1.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.4.1.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.4.1.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.4.1.1.8.5 Transmit-Only
                6. 12.1.5.4.1.1.8.6 Receive-Only With Word Count
                7. 12.1.5.4.1.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.4.1.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.4.1.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.4.1.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.4.1.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.4.1.1.9.4 Transmit-and-Receive Procedure – Polling Method
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Ports
        2. 12.1.6.2 UART Environment
        3. 12.1.6.3 UART Functional Description
          1. 12.1.6.3.1 UART Block Diagram
          2. 12.1.6.3.2 UART Clock Configuration
          3. 12.1.6.3.3 UART Software Reset
            1. 12.1.6.3.3.1 Independent TX/RX
          4. 12.1.6.3.4 UART Power Management
            1. 12.1.6.3.4.1 UART Mode Power Management
              1. 12.1.6.3.4.1.1 Module Power Saving
              2. 12.1.6.3.4.1.2 System Power Saving
            2. 12.1.6.3.4.2 IrDA Mode Power Management
              1. 12.1.6.3.4.2.1 Module Power Saving
              2. 12.1.6.3.4.2.2 System Power Saving
            3. 12.1.6.3.4.3 CIR Mode Power Management
              1. 12.1.6.3.4.3.1 Module Power Saving
              2. 12.1.6.3.4.3.2 System Power Saving
            4. 12.1.6.3.4.4 Local Power Management
          5. 12.1.6.3.5 UART Interrupt Requests
            1. 12.1.6.3.5.1 UART Mode Interrupt Management
              1. 12.1.6.3.5.1.1 UART Interrupts
              2. 12.1.6.3.5.1.2 Wake-Up Interrupt
            2. 12.1.6.3.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.3.5.2.1 IrDA Interrupts
              2. 12.1.6.3.5.2.2 Wake-Up Interrupts
            3. 12.1.6.3.5.3 CIR Mode Interrupt Management
              1. 12.1.6.3.5.3.1 CIR Interrupts
              2. 12.1.6.3.5.3.2 Wake-Up Interrupts
          6. 12.1.6.3.6 UART FIFO Management
            1. 12.1.6.3.6.1 FIFO Trigger
              1. 12.1.6.3.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.3.6.1.2 Receive FIFO Trigger
            2. 12.1.6.3.6.2 FIFO Interrupt Mode
            3. 12.1.6.3.6.3 FIFO Polled Mode Operation
            4. 12.1.6.3.6.4 FIFO DMA Mode Operation
              1. 12.1.6.3.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.3.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.3.6.4.3 DMA Transmission
              4. 12.1.6.3.6.4.4 DMA Reception
          7. 12.1.6.3.7 UART Mode Selection
            1. 12.1.6.3.7.1 Register Access Modes
              1. 12.1.6.3.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.3.7.1.2 Register Access Submode
              3. 12.1.6.3.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.3.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.3.7.2.1 Registers Available for the UART Function
              2. 12.1.6.3.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.3.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.3.8 UART Protocol Formatting
            1. 12.1.6.3.8.1 UART Mode
              1. 12.1.6.3.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.3.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.3.8.1.3 UART Data Formatting
                1. 12.1.6.3.8.1.3.1 Frame Formatting
                2. 12.1.6.3.8.1.3.2 Hardware Flow Control
                3. 12.1.6.3.8.1.3.3 Software Flow Control
                  1. 1.6.3.8.1.3.3.1 Receive (RX)
                  2. 1.6.3.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.3.8.1.3.4 Autobauding Modes
                5. 12.1.6.3.8.1.3.5 Error Detection
                6. 12.1.6.3.8.1.3.6 Overrun During Receive
                7. 12.1.6.3.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.3.8.1.3.7.1 Time-Out Counter
                  2. 1.6.3.8.1.3.7.2 Break Condition
            2. 12.1.6.3.8.2 RS-485 Mode
              1. 12.1.6.3.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.3.8.3 IrDA Mode
              1. 12.1.6.3.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.3.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.3.8.3.3 IrDA Data Formatting
                1. 12.1.6.3.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.3.8.3.3.2  IrDA Reception Control
                3. 12.1.6.3.8.3.3.3  IR Address Checking
                4. 12.1.6.3.8.3.3.4  Frame Closing
                5. 12.1.6.3.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.3.8.3.3.6  Error Detection
                7. 12.1.6.3.8.3.3.7  Underrun During Transmission
                8. 12.1.6.3.8.3.3.8  Overrun During Receive
                9. 12.1.6.3.8.3.3.9  Status FIFO
                10. 12.1.6.3.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.3.8.3.3.11 Time-guard
              4. 12.1.6.3.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.3.8.3.4.1 Abort Sequence
                2. 12.1.6.3.8.3.4.2 Pulse Shaping
                3. 12.1.6.3.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.3.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.3.8.4 CIR Mode
              1. 12.1.6.3.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.3.8.4.2 CIR Data Formatting
                1. 12.1.6.3.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.3.8.4.2.2 CIR Transmission
                3. 12.1.6.3.8.4.2.3 CIR Reception
        4. 12.1.6.4 UART Programming Guide
          1. 12.1.6.4.1 UART Mode selection
          2. 12.1.6.4.2 UART Submode selection
          3. 12.1.6.4.3 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.4.3.1 DMA mode Settings
            2. 12.1.6.4.3.2 FIFO Trigger Settings
          4. 12.1.6.4.4 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.4.4.1 Baud rate settings
            2. 12.1.6.4.4.2 Interrupt settings
            3. 12.1.6.4.4.3 Protocol settings
            4. 12.1.6.4.4.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.4.4.5 UART Multi-drop Parity Address Match Mode Configuration
          5. 12.1.6.4.5 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.4.5.1 Hardware Flow Control Configuration
            2. 12.1.6.4.5.2 Software Flow Control Configuration
          6. 12.1.6.4.6 IrDA Programming Model
            1. 12.1.6.4.6.1 SIR mode
              1. 12.1.6.4.6.1.1 Receive
              2. 12.1.6.4.6.1.2 Transmit
            2. 12.1.6.4.6.2 MIR mode
              1. 12.1.6.4.6.2.1 Receive
              2. 12.1.6.4.6.2.2 Transmit
            3. 12.1.6.4.6.3 FIR mode
              1. 12.1.6.4.6.3.1 Receive
              2. 12.1.6.4.6.3.2 Transmit
    2. 12.2  High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (CPSW)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 CPSW Features
          2. 12.2.1.1.2 Terminology
          3. 12.2.1.1.3 MCU_CPSW0 Ports
        2. 12.2.1.2 CPSW Functional Description
          1. 12.2.1.2.1 Functional Block Diagram
          2. 12.2.1.2.2 CPSW Ports
            1. 12.2.1.2.2.1 Interface Mode Selection
          3. 12.2.1.2.3 Clocking
            1. 12.2.1.2.3.1 Subsystem Clocking
            2. 12.2.1.2.3.2 Interface Clocking
              1. 12.2.1.2.3.2.1 RGMII Interface Clocking
              2. 12.2.1.2.3.2.2 RMII Interface Clocking
              3. 12.2.1.2.3.2.3 MDIO Clocking
          4. 12.2.1.2.4 Software IDLE
          5. 12.2.1.2.5 Interrupt Functionality
            1. 12.2.1.2.5.1 EVNT_PEND Interrupt
            2. 12.2.1.2.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.2.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.2.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.2.5.5 MDIO Interrupts
          6. 12.2.1.2.6 CPSW_2G
            1. 12.2.1.2.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.2.6.1.1  Error Handling
              2. 12.2.1.2.6.1.2  Bypass Operations
              3. 12.2.1.2.6.1.3  OUI Deny or Accept
              4. 12.2.1.2.6.1.4  Statistics Counting
              5. 12.2.1.2.6.1.5  Automotive Security Features
              6. 12.2.1.2.6.1.6  CPSW Switching Solutions
                1. 12.2.1.2.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.2.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.2.6.1.7.1 InterVLAN Routing
                2. 12.2.1.2.6.1.7.2 OAM Operations
              8. 12.2.1.2.6.1.8  Supervisory packets
              9. 12.2.1.2.6.1.9  Address Table Entry
                1. 12.2.1.2.6.1.9.1 Free Table Entry
                2. 12.2.1.2.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.2.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.2.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.2.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.2.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.2.6.1.9.7 VLAN Table Entry
              10. 12.2.1.2.6.1.10 ALE Policing and Classification
                1. 12.2.1.2.6.1.10.1 ALE Classification
                  1. 2.1.2.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.2.6.1.11 DSCP
              12. 12.2.1.2.6.1.12 Packet Forwarding Processes
                1. 12.2.1.2.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.2.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.2.6.1.12.3 Egress Process
                4. 12.2.1.2.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.2.6.1.12.4.1 Learning Process
                  2. 2.1.2.6.1.12.4.2 Updating Process
                  3. 2.1.2.6.1.12.4.3 Touching Process
              13. 12.2.1.2.6.1.13 VLAN Aware Mode
              14. 12.2.1.2.6.1.14 VLAN Unaware Mode
            2. 12.2.1.2.6.2  Packet Priority Handling
              1. 12.2.1.2.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.2.6.3  CPPI Port Ingress
            4. 12.2.1.2.6.4  Packet CRC Handling
              1. 12.2.1.2.6.4.1 Transmit VLAN Processing
                1. 12.2.1.2.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.2.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.2.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.2.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.2.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.2.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.2.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.2.6.5  FIFO Memory Control
            6. 12.2.1.2.6.6  FIFO Transmit Queue Control
              1. 12.2.1.2.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.2.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.2.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.2.6.7.1 IET Configuration
            8. 12.2.1.2.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.2.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.2.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.2.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.2.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.2.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.2.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.2.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.2.6.9  Audio Video Bridging
              1. 12.2.1.2.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.2.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.2.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.2.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.2.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.2.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.2.6.10 Ethernet MAC Sliver
              1. 12.2.1.2.6.10.1  CRC Insertion
              2. 12.2.1.2.6.10.2  MTXER
              3. 12.2.1.2.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.1.2.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.1.2.6.10.5  Back Off
              6. 12.2.1.2.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.1.2.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.1.2.6.10.8  RMII Interface
                1. 12.2.1.2.6.10.8.1 Features
                2. 12.2.1.2.6.10.8.2 RMII Receive (RX)
                3. 12.2.1.2.6.10.8.3 RMII Transmit (TX)
              9. 12.2.1.2.6.10.9  RGMII Interface
                1. 12.2.1.2.6.10.9.1 Features
                2. 12.2.1.2.6.10.9.2 RGMII Receive (RX)
                3. 12.2.1.2.6.10.9.3 In-Band Mode of Operation
                4. 12.2.1.2.6.10.9.4 Forced Mode of Operation
                5. 12.2.1.2.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.1.2.6.10.10 Frame Classification
              11. 12.2.1.2.6.10.11 Receive FIFO Architecture
            11. 12.2.1.2.6.11 Embedded Memories
            12. 12.2.1.2.6.12 Memory Error Detection and Correction
              1. 12.2.1.2.6.12.1 Packet Header ECC
              2. 12.2.1.2.6.12.2 Packet Protect CRC
              3. 12.2.1.2.6.12.3 Aggregator RAM Control
            13. 12.2.1.2.6.13 Ethernet Port Flow Control
              1. 12.2.1.2.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.2.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.2.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.2.6.13.2 Flow Control Trigger
              3. 12.2.1.2.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.2.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.2.6.15 Ethernet Switch Latency
            16. 12.2.1.2.6.16 MAC Emulation Control
            17. 12.2.1.2.6.17 MAC Command IDLE
            18. 12.2.1.2.6.18 CPSW Network Statistics
              1. 12.2.1.2.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.2.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.2.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.2.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.2.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.2.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.2.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.2.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.2.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.2.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.2.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.2.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.2.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.2.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.2.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.2.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.2.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.2.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.2.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.2.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.2.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.2.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.2.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.2.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.2.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.2.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.2.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.2.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.2.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.2.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.2.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.2.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.2.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.2.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.2.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.2.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.2.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.2.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.2.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.2.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.2.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.2.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.2.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.2.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.2.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.2.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.2.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.2.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.2.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.2.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.2.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.2.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.2.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.2.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.2.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.2.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.2.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.2.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.2.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.2.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.2.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.2.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.2.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.2.6.18.10 2312
          7. 12.2.1.2.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.2.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.2.7.2  CPTS Architecture
            3. 12.2.1.2.7.3  CPTS Initialization
            4. 12.2.1.2.7.4  32-bit Time Stamp Value
            5. 12.2.1.2.7.5  64-bit Time Stamp Value
            6. 12.2.1.2.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.2.7.7  64-bit Timestamp PPM
            8. 12.2.1.2.7.8  Event FIFO
            9. 12.2.1.2.7.9  Timestamp Compare Output
              1. 12.2.1.2.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.2.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.2.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.2.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.2.7.10 Timestamp Sync Output
            11. 12.2.1.2.7.11 Timestamp GENFn Output
              1. 12.2.1.2.7.11.1 GENFn Nudge
              2. 12.2.1.2.7.11.2 GENFn PPM
            12. 12.2.1.2.7.12 Timestamp ESTFn
            13. 12.2.1.2.7.13 Time Sync Events
              1. 12.2.1.2.7.13.1 Time Stamp Push Event
              2. 12.2.1.2.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.2.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.2.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.2.7.13.5 Ethernet Port Events
                1. 12.2.1.2.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.2.7.13.5.2 Ethernet Port Transmit Event
            14. 12.2.1.2.7.14 Timestamp Compare Event
              1. 12.2.1.2.7.14.1 32-Bit Mode
              2. 12.2.1.2.7.14.2 64-Bit Mode
            15. 12.2.1.2.7.15 Host Transmit Event
            16. 12.2.1.2.7.16 CPTS Interrupt Handling
          8. 12.2.1.2.8 CPPI Streaming Packet Interface
            1. 12.2.1.2.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.2.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.2.8.3 CPPI Checksum Offload
              1. 12.2.1.2.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.2.8.3.1.1 IPV4 UDP
                2. 12.2.1.2.8.3.1.2 IPV4 TCP
                3. 12.2.1.2.8.3.1.3 IPV6 UDP
                4. 12.2.1.2.8.3.1.4 IPV6 TCP
            4. 12.2.1.2.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.2.8.5 Egress Packet Operations
          9. 12.2.1.2.9 MII Management Interface (MDIO)
            1. 12.2.1.2.9.1 MDIO Frame Formats
            2. 12.2.1.2.9.2 MDIO Functional Description
        3. 12.2.1.3 CPSW Programming Guide
          1. 12.2.1.3.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.3.2 CPSW Reset
          3. 12.2.1.3.3 MDIO Software Interface
            1. 12.2.1.3.3.1 Initializing the MDIO Module
            2. 12.2.1.3.3.2 Writing Data To a PHY Register
            3. 12.2.1.3.3.3 Reading Data From a PHY Register
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
          4. 12.2.2.1.4 CPSW Ports
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Functional Description
          1. 12.2.2.3.1 Functional Block Diagram
          2. 12.2.2.3.2 CPSW Ports
            1. 12.2.2.3.2.1 Interface Mode Selection
          3. 12.2.2.3.3 Clocking
            1. 12.2.2.3.3.1 Subsystem Clocking
            2. 12.2.2.3.3.2 Interface Clocking
              1. 12.2.2.3.3.2.1 RGMII Interface Clocking
              2. 12.2.2.3.3.2.2 RMII Interface Clocking
              3. 12.2.2.3.3.2.3 MDIO Clocking
          4. 12.2.2.3.4 Software IDLE
          5. 12.2.2.3.5 Interrupt Functionality
            1. 12.2.2.3.5.1 EVNT_PEND Interrupt
            2. 12.2.2.3.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.3.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.3.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.3.5.5 MDIO Interrupts
          6. 12.2.2.3.6 CPSW_9G
            1. 12.2.2.3.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.3.6.1.1  Error Handling
              2. 12.2.2.3.6.1.2  Bypass Operations
              3. 12.2.2.3.6.1.3  OUI Deny or Accept
              4. 12.2.2.3.6.1.4  Statistics Counting
              5. 12.2.2.3.6.1.5  Automotive Security Features
              6. 12.2.2.3.6.1.6  CPSW Switching Solutions
                1. 12.2.2.3.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.3.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.3.6.1.7.1 InterVLAN Routing
                2. 12.2.2.3.6.1.7.2 OAM Operations
              8. 12.2.2.3.6.1.8  Supervisory packets
              9. 12.2.2.3.6.1.9  Address Table Entry
                1. 12.2.2.3.6.1.9.1  Free Table Entry
                2. 12.2.2.3.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.3.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.3.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.3.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.3.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.3.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.3.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.3.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.3.6.1.9.10 EtherType Table Entry
                11. 12.2.2.3.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.3.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.3.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.3.6.1.10 Multicast Address
                1. 12.2.2.3.6.1.10.1 Multicast Ranges
              11. 12.2.2.3.6.1.11 Supervisory Packets
              12. 12.2.2.3.6.1.12 Aging and Auto Aging
              13. 12.2.2.3.6.1.13 ALE Policing and Classification
                1. 12.2.2.3.6.1.13.1 ALE Policing
                2. 12.2.2.3.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.3.6.1.13.3 ALE Classification
                  1. 2.2.3.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.3.6.1.14 Mirroring
              15. 12.2.2.3.6.1.15 Trunking
              16. 12.2.2.3.6.1.16 DSCP
              17. 12.2.2.3.6.1.17 Packet Forwarding Processes
                1. 12.2.2.3.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.3.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.3.6.1.17.3 Egress Process
                4. 12.2.2.3.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.3.6.1.17.4.1 Learning Process
                  2. 2.2.3.6.1.17.4.2 Updating Process
                  3. 2.2.3.6.1.17.4.3 Touching Process
              18. 12.2.2.3.6.1.18 VLAN Aware Mode
              19. 12.2.2.3.6.1.19 VLAN Unaware Mode
            2. 12.2.2.3.6.2  Packet Priority Handling
              1. 12.2.2.3.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.3.6.3  CPPI Port Ingress
            4. 12.2.2.3.6.4  Packet CRC Handling
              1. 12.2.2.3.6.4.1 Transmit VLAN Processing
                1. 12.2.2.3.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.3.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.3.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.3.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.3.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.3.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.3.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.3.6.5  FIFO Memory Control
            6. 12.2.2.3.6.6  FIFO Transmit Queue Control
              1. 12.2.2.3.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.3.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.3.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.3.6.7.1 IET Configuration
            8. 12.2.2.3.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.3.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.3.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.3.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.3.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.3.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.3.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.3.6.9  Audio Video Bridging
              1. 12.2.2.3.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.3.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.3.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.3.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.3.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.3.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.3.6.10 Ethernet MAC Sliver
              1. 12.2.2.3.6.10.1  CRC Insertion
              2. 12.2.2.3.6.10.2  MTXER
              3. 12.2.2.3.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.3.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.3.6.10.5  Back Off
              6. 12.2.2.3.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.3.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.3.6.10.8  RMII Interface
                1. 12.2.2.3.6.10.8.1 Features
                2. 12.2.2.3.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.3.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.3.6.10.9  RGMII Interface
                1. 12.2.2.3.6.10.9.1 Features
                2. 12.2.2.3.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.3.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.3.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.3.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.3.6.10.10 Frame Classification
              11. 12.2.2.3.6.10.11 Receive FIFO Architecture
            11. 12.2.2.3.6.11 Embedded Memories
            12. 12.2.2.3.6.12 Memory Error Detection and Correction
              1. 12.2.2.3.6.12.1 Packet Header ECC
              2. 12.2.2.3.6.12.2 Packet Protect CRC
              3. 12.2.2.3.6.12.3 Aggregator RAM Control
            13. 12.2.2.3.6.13 Ethernet Port Flow Control
              1. 12.2.2.3.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.3.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.3.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.3.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.3.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.3.6.14 PFC Trigger Rules
              1. 12.2.2.3.6.14.1 Destination Based Rule
              2. 12.2.2.3.6.14.2 Sum of Outflows Rule
              3. 12.2.2.3.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.3.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.3.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.3.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.3.6.16 Ethernet Switch Latency
            17. 12.2.2.3.6.17 MAC Emulation Control
            18. 12.2.2.3.6.18 MAC Command IDLE
            19. 12.2.2.3.6.19 CPSW Network Statistics
              1. 12.2.2.3.6.19.1 Rx-only Statistics Descriptions
                1. 12.2.2.3.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.3.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.3.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.3.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.3.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.3.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.3.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.3.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.3.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.3.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.3.6.19.1.11 RX IPG Error
                12. 12.2.2.3.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.3.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.3.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.3.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.3.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.3.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.3.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.3.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.3.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.3.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.3.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.3.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.3.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.3.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.3.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.3.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.3.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.3.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.3.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.3.6.19.2 ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.3.6.19.3 ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.3.6.19.4 IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.3.6.19.5 IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.3.6.19.6 IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.3.6.19.7 IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.3.6.19.8 Tx-only Statistics Descriptions
                1. 12.2.2.3.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.3.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.3.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.3.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.3.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.3.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.3.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.3.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.3.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.3.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.3.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.3.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.3.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.3.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.3.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.3.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.3.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.3.6.19.9 Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.3.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.3.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.3.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.3.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.3.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.3.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.3.6.19.9.7 Net Octets (Offset = 3A080h)
          7. 12.2.2.3.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.3.7.1  CPSW0 CPTS Integration
            2. 12.2.2.3.7.2  CPTS Architecture
            3. 12.2.2.3.7.3  CPTS Initialization
            4. 12.2.2.3.7.4  32-bit Time Stamp Value
            5. 12.2.2.3.7.5  64-bit Time Stamp Value
            6. 12.2.2.3.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.3.7.7  64-bit Timestamp PPM
            8. 12.2.2.3.7.8  Event FIFO
            9. 12.2.2.3.7.9  Timestamp Compare Output
              1. 12.2.2.3.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.3.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.3.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.3.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.3.7.10 Timestamp Sync Output
            11. 12.2.2.3.7.11 Timestamp GENFn Output
              1. 12.2.2.3.7.11.1 GENFn Nudge
              2. 12.2.2.3.7.11.2 GENFn PPM
            12. 12.2.2.3.7.12 Timestamp ESTFn
            13. 12.2.2.3.7.13 Time Sync Events
              1. 12.2.2.3.7.13.1 Time Stamp Push Event
              2. 12.2.2.3.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.3.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.3.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.3.7.13.5 Ethernet Port Events
                1. 12.2.2.3.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.3.7.13.5.2 Ethernet Port Transmit Event
            14. 12.2.2.3.7.14 Timestamp Compare Event
              1. 12.2.2.3.7.14.1 32-Bit Mode
              2. 12.2.2.3.7.14.2 64-Bit Mode
            15. 12.2.2.3.7.15 Host Transmit Event
            16. 12.2.2.3.7.16 CPTS Interrupt Handling
          8. 12.2.2.3.8 CPPI Streaming Packet Interface
            1. 12.2.2.3.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_9G Egress)
            2. 12.2.2.3.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.3.8.3 CPPI Checksum Offload
              1. 12.2.2.3.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.3.8.3.1.1 IPV4 UDP
                2. 12.2.2.3.8.3.1.2 IPV4 TCP
                3. 12.2.2.3.8.3.1.3 IPV6 UDP
                4. 12.2.2.3.8.3.1.4 IPV6 TCP
            4. 12.2.2.3.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.3.8.5 Egress Packet Operations
          9. 12.2.2.3.9 MII Management Interface (MDIO)
            1. 12.2.2.3.9.1 MDIO Frame Formats
            2. 12.2.2.3.9.2 MDIO Functional Description
        4. 12.2.2.4 CPSW0 Programming Guide
          1. 12.2.2.4.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.4.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.4.3 MDIO Software Interface
            1. 12.2.2.4.3.1 Initializing the MDIO Module
            2. 12.2.2.4.3.2 Writing Data To a PHY Register
            3. 12.2.2.4.3.3 Reading Data From a PHY Register
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Ports
        2. 12.2.3.2 PCIe Environment
        3. 12.2.3.3 PCIe Subsystem Functional Description
          1. 12.2.3.3.1  PCIe Subsystem Block Diagram
            1. 12.2.3.3.1.1 PCIe Core Module
            2. 12.2.3.3.1.2 PCIe PHY Interface
            3. 12.2.3.3.1.3 CBA Infrastructure
            4. 12.2.3.3.1.4 VBUSM to AXI Bridges
            5. 12.2.3.3.1.5 AXI to VBUSM Bridges
            6. 12.2.3.3.1.6 VBUSP to APB Bridge
            7. 12.2.3.3.1.7 Custom Logic
          2. 12.2.3.3.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.3.2.1 PCIe Conventional Reset
            2. 12.2.3.3.2.2 PCIe Function Level Reset
            3. 12.2.3.3.2.3 PCIe Reset Isolation
              1. 12.2.3.3.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.3.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.3.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.3.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.3.2.4 PCIe Reset Limitations
            5. 12.2.3.3.2.5 PCIe Reset Requirements
          3. 12.2.3.3.3  PCIe Subsystem Power Management
            1. 12.2.3.3.3.1 CBA Power Management
          4. 12.2.3.3.4  PCIe Subsystem Interrupts
            1. 12.2.3.3.4.1 Interrupts Aggregation
            2. 12.2.3.3.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.3.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.3.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.3.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.3.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.3.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.3.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.3.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.3.4.3.5 PTM Valid Interrupt
            4. 12.2.3.3.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.3.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.3.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.3.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.3.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.3.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.3.4.6.1 PCIe Local Interrupt
              2. 12.2.3.3.4.6.2 PHY Interrupt
              3. 12.2.3.3.4.6.3 Link down Interrupt
              4. 12.2.3.3.4.6.4 Transaction Error Interrupts
              5. 12.2.3.3.4.6.5 Power Management Event Interrupt
              6. 12.2.3.3.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.3.4.7 ECC Aggregator Interrupts
            8. 12.2.3.3.4.8 CPTS Interrupt
          5. 12.2.3.3.5  PCIe Subsystem DMA Support
            1. 12.2.3.3.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.3.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.3.6  PCIe Subsystem Transactions
            1. 12.2.3.3.6.1 PCIe Supported Transactions
            2. 12.2.3.3.6.2 PCIe Transaction Limitations
          7. 12.2.3.3.7  PCIe Subsystem Address Translation
            1. 12.2.3.3.7.1 PCIe Inbound Address Translation
              1. 12.2.3.3.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.3.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.3.7.2 PCIe Outbound Address Translation
              1. 12.2.3.3.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.3.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.3.8.1 End Point SR-IOV Support
            2. 12.2.3.3.8.2 Root Port ATS Support
            3. 12.2.3.3.8.3 VirtID Mapping
          9. 12.2.3.3.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.3.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.3.11 PCIe Subsystem Loopback
            1. 12.2.3.3.11.1 PCIe PIPE Loopback
              1. 12.2.3.3.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.3.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.3.12 PCIe Subsystem Error Handling
            1. 12.2.3.3.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.3.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.3.13.1 PCIe Parity
            2. 12.2.3.3.13.2 ECC Aggregators
            3. 12.2.3.3.13.3 RAM ECC Inversion
          14. 12.2.3.3.14 LTSSM State Encoding
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Ports
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Functional Description
          1. 12.2.4.3.1 USB Type-C Connector Support
          2. 12.2.4.3.2 USB Controller Reset
          3. 12.2.4.3.3 Overcurrent Detection
          4. 12.2.4.3.4 Top-Level Initialization Sequence
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
          3. 12.2.5.1.3 SerDes Ports
            1. 12.2.5.1.3.1 WIZ Settings
              1. 12.2.5.1.3.1.1 Interface Selection
              2. 12.2.5.1.3.1.2 USB3.0 Double Muxing
              3. 12.2.5.1.3.1.3 Hyperlink SERDES Double Muxing
              4. 12.2.5.1.3.1.4 CPSW Channel and SERDES IP Mapping
              5. 12.2.5.1.3.1.5 ACSPCIe Reference Clock Selection
              6. 12.2.5.1.3.1.6 Internal Reference Clock Selection
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Functional Description
          1. 12.2.5.3.1 SerDes Block Diagram
    3. 12.3  Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 Flash Ports
        2. 12.3.1.2 FSS Environment
        3. 12.3.1.3 FSS Functional Description
          1. 12.3.1.3.1 FSS Block Diagram
          2. 12.3.1.3.2 FSS ECC Support
          3. 12.3.1.3.3 FSS Modes of Operation
          4. 12.3.1.3.4 FSS Regions
            1. 12.3.1.3.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.3.5 FSS Memory Regions
        4. 12.3.1.4 FSS Programming Guide
          1. 12.3.1.4.1 FSS Initialization Sequence
          2. 12.3.1.4.2 FSS Real-Time Operation
          3. 12.3.1.4.3 FSS Power Up/Down Sequence
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Ports
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Functional Description
          1. 12.3.2.3.1  OSPI Block Diagram
            1. 12.3.2.3.1.1 Data Slave Interface
            2. 12.3.2.3.1.2 Configuration Slave Interface
            3. 12.3.2.3.1.3 OSPI Clock Domains
          2. 12.3.2.3.2  OSPI Modes
            1. 12.3.2.3.2.1 Read Data Capture
              1. 12.3.2.3.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.3.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.3.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.3.2.2 External Pull Down on DQS
          3. 12.3.2.3.3  OSPI Power Management
          4. 12.3.2.3.4  Auto HW Polling
          5. 12.3.2.3.5  Flash Reset
          6. 12.3.2.3.6  OSPI Memory Regions
          7. 12.3.2.3.7  OSPI Interrupt Requests
          8. 12.3.2.3.8  OSPI Data Interface
            1. 12.3.2.3.8.1 Data Interface Address Remapping
            2. 12.3.2.3.8.2 Write Protection
            3. 12.3.2.3.8.3 Access Forwarding
          9. 12.3.2.3.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.3.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.3.10.1 Indirect Read Controller
              1. 12.3.2.3.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.3.10.2 Indirect Write Controller
              1. 12.3.2.3.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.3.10.3 Indirect Access Queuing
            4. 12.3.2.3.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.3.10.5 Accessing the SRAM
          11. 12.3.2.3.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.3.11.1 Servicing a STIG Request
          12. 12.3.2.3.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.3.13 OSPI Command Translation
          14. 12.3.2.3.14 Selecting the Flash Instruction Type
          15. 12.3.2.3.15 OSPI Data Integrity
          16. 12.3.2.3.16 OSPI PHY Module
            1. 12.3.2.3.16.1 PHY Pipeline Mode
            2. 12.3.2.3.16.2 Read Data Capturing by the PHY Module
        4. 12.3.2.4 OSPI Programming Guide
          1. 12.3.2.4.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.4.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.4.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.4.4 Using SPI Legacy Mode
          5. 12.3.2.4.5 Entering XIP Mode from POR
          6. 12.3.2.4.6 Entering XIP Mode Otherwise
          7. 12.3.2.4.7 Exiting XIP Mode
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 Hyperbus Ports
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Functional Description
          1. 12.3.3.3.1 HyperBus Interrupts
          2. 12.3.3.3.2 HyperBus ECC Support
            1. 12.3.3.3.2.1 ECC Aggregator
          3. 12.3.3.3.3 HyperBus Internal FIFOs
          4. 12.3.3.3.4 HyperBus Data Regions
          5. 12.3.3.3.5 HyperBus True Continuous Read (TCR) Mode
        4. 12.3.3.4 HyperBus Programming Guide
          1. 12.3.3.4.1 HyperBus Initialization Sequence
            1. 12.3.3.4.1.1 HyperFlash Access
            2. 12.3.3.4.1.2 HyperRAM Access
          2. 12.3.3.4.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.4.3 HyperBus Power Up/Down Sequence
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Ports
        2. 12.3.4.2 GPMC Environment
        3. 12.3.4.3 GPMC Functional Description
          1. 12.3.4.3.1  GPMC Block Diagram
          2. 12.3.4.3.2  GPMC Clock Configuration
          3. 12.3.4.3.3  GPMC Power Management
          4. 12.3.4.3.4  GPMC Interrupt Requests
          5. 12.3.4.3.5  GPMC Interconnect Port Interface
          6. 12.3.4.3.6  GPMC Address and Data Bus
            1. 12.3.4.3.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.3.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.3.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.3.7.2 Access Protocol
              1. 12.3.4.3.7.2.1 Supported Devices
              2. 12.3.4.3.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.3.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.3.7.3 External Signals
              1. 12.3.4.3.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.3.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.3.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.3.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.3.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.3.7.3.1.5 Wait With NAND Device
                6. 12.3.4.3.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.3.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.3.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.3.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.3.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.3.7.3.2 DIR Pin
              3. 12.3.4.3.7.3.3 Reset
              4. 12.3.4.3.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.3.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.3.7.4 Error Handling
          8. 12.3.4.3.8  GPMC Timing Setting
            1. 12.3.4.3.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.3.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.3.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.3.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.3.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.3.8.6  GPMC_CLKOUT
            7. 12.3.4.3.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.3.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.3.8.8.1 Access Time on Read Access
              2. 12.3.4.3.8.8.2 Access Time on Write Access
            9. 12.3.4.3.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.3.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.3.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.3.8.10 Bus Keeping Support
          9. 12.3.4.3.9  GPMC NOR Access Description
            1. 12.3.4.3.9.1 Asynchronous Access Description
              1. 12.3.4.3.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.3.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.3.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.3.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.3.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.3.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.3.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.3.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.3.9.2 Synchronous Access Description
              1. 12.3.4.3.9.2.1 Synchronous Single Read
              2. 12.3.4.3.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.3.9.2.3 Synchronous Single Write
              4. 12.3.4.3.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.3.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.3.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.3.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.3.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.3.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.3.9.4 Page and Burst Support
            5. 12.3.4.3.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.3.10 GPMC pSRAM Access Specificities
          11. 12.3.4.3.11 GPMC NAND Access Description
            1. 12.3.4.3.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.3.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.3.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.3.11.1.3 Command Latch Cycle
              4. 12.3.4.3.11.1.4 Address Latch Cycle
              5. 12.3.4.3.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.3.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.3.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.3.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.3.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.3.11.2 NAND Device-Ready Pin
              1. 12.3.4.3.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.3.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.3.11.3 ECC Calculator
              1. 12.3.4.3.11.3.1 Hamming Code
                1. 12.3.4.3.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.3.11.3.1.2 ECC Enabling
                3. 12.3.4.3.11.3.1.3 ECC Computation
                4. 12.3.4.3.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.3.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.3.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.3.11.3.2 BCH Code
                1. 12.3.4.3.11.3.2.1 Requirements
                2. 12.3.4.3.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.3.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.3.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.3.11.3.2.2.3 Wrapping Modes
                    1. 4.3.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.3.11.3.2.2.3.2  Mode 0x1
                    3. 4.3.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.3.11.3.2.2.3.4  Mode 0x2
                    5. 4.3.11.3.2.2.3.5  Mode 0x3
                    6. 4.3.11.3.2.2.3.6  Mode 0x7
                    7. 4.3.11.3.2.2.3.7  Mode 0x8
                    8. 4.3.11.3.2.2.3.8  Mode 0x4
                    9. 4.3.11.3.2.2.3.9  Mode 0x9
                    10. 4.3.11.3.2.2.3.10 Mode 0x5
                    11. 4.3.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.3.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.3.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.3.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.3.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.3.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.3.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.3.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.3.11.4.2 Prefetch Mode
              3. 12.3.4.3.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.3.11.4.4 Write-Posting Mode
              5. 12.3.4.3.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.3.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.3.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.3.12 GPMC Memory Regions
          13. 12.3.4.3.13 GPMC Use Cases and Tips
            1. 12.3.4.3.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.3.13.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.3.13.1.2 Typical GPMC Setup
                1. 12.3.4.3.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.3.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.3.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.3.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.3.13.2.1 Supported Memories or Devices
                1. 12.3.4.3.13.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.3.13.2.1.2 NAND Interface Protocol
                3. 12.3.4.3.13.2.1.3 NOR Interface Protocol
                4. 12.3.4.3.13.2.1.4 Other Technologies
        4. 12.3.4.4 GPMC Basic Programming Model
          1. 12.3.4.4.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.4.2 GPMC Initialization
          3. 12.3.4.4.3 GPMC Configuration in NOR Mode
          4. 12.3.4.4.4 GPMC Configuration in NAND Mode
          5. 12.3.4.4.5 Set Memory Access
          6. 12.3.4.4.6 GPMC Timing Parameters
            1. 12.3.4.4.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.4.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.4.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.4.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Ports
        2. 12.3.5.2 ELM Functional Description
          1. 12.3.5.2.1 ELM Software Reset
          2. 12.3.5.2.2 ELM Power Management
          3. 12.3.5.2.3 ELM Interrupt Requests
          4. 12.3.5.2.4 ELM Processing Initialization
          5. 12.3.5.2.5 ELM Processing Sequence
          6. 12.3.5.2.6 ELM Processing Completion
        3. 12.3.5.3 ELM Basic Programming Model
          1. 12.3.5.3.1 ELM Low-Level Programming Model
            1. 12.3.5.3.1.1 Processing Initialization
            2. 12.3.5.3.1.2 Read Results
            3. 12.3.5.3.1.3 2990
          2. 12.3.5.3.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.3.3 Use Case: ELM Used in Page Mode
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Ports
        2. 12.3.6.2 MMCSD Environment
        3. 12.3.6.3 MMCSD Functional Description
          1. 12.3.6.3.1 Block Diagram
          2. 12.3.6.3.2 Memory Regions
          3. 12.3.6.3.3 Interrupt Requests
          4. 12.3.6.3.4 ECC Support
            1. 12.3.6.3.4.1 ECC Aggregator
          5. 12.3.6.3.5 Advanced DMA
        4. 12.3.6.4 MMCSD Programming Guide
          1. 12.3.6.4.1 Sequences
            1. 12.3.6.4.1.1  SD Card Detection
            2. 12.3.6.4.1.2  SD Clock Control
              1. 12.3.6.4.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.4.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.4.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.4.1.3  SD Bus Power Control
            4. 12.3.6.4.1.4  Changing Bus Width
            5. 12.3.6.4.1.5  Timeout Setting on DAT Line
            6. 12.3.6.4.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.4.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.4.1.7  SD Transaction Generation
              1. 12.3.6.4.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.4.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.4.1.7.1.2 The Sequence to Finalize a Command
              2. 12.3.6.4.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.4.1.7.2.1 Not using DMA
                2. 12.3.6.4.1.7.2.2 Using SDMA
                3. 12.3.6.4.1.7.2.3 Using ADMA
            8. 12.3.6.4.1.8  Abort Transaction
              1. 12.3.6.4.1.8.1 Asynchronous Abort
              2. 12.3.6.4.1.8.2 Synchronous Abort
            9. 12.3.6.4.1.9  Changing Bus Speed Mode
            10. 12.3.6.4.1.10 Error Recovery
              1. 12.3.6.4.1.10.1 Error Interrupt Recovery
              2. 12.3.6.4.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.4.1.11 Wakeup Control (Optional)
            12. 12.3.6.4.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.4.1.12.1 Suspend Sequence
              2. 12.3.6.4.1.12.2 Resume Sequence
              3. 12.3.6.4.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.4.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.4.2 Driver Flow Sequence
            1. 12.3.6.4.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.4.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.4.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.4.2.2 Boot Operation
              1. 12.3.6.4.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.4.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.4.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.4.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.4.2.3.1 Sampling Clock Tuning
              2. 12.3.6.4.2.3.2 Tuning Modes
              3. 12.3.6.4.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.4.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.4.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.4.2.4.2 Task Issuance Sequence
              3. 12.3.6.4.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.4.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.4.2.4.5 Error Detect and Recovery when CQ is enabled
      7. 12.3.7 Universal Flash Storage (UFS) Interface
        1. 12.3.7.1 UFS Overview
          1. 12.3.7.1.1 UFS Features
          2. 12.3.7.1.2 UFS Ports
        2. 12.3.7.2 UFS Environment
        3. 12.3.7.3 UFS Functional Description
          1. 12.3.7.3.1 UFS Block Diagrams
          2. 12.3.7.3.2 UFS ECC Support
        4. 12.3.7.4 UFS Programming Guide
          1. 12.3.7.4.1 UFS Start-Up Sequence
            1. 12.3.7.4.1.1 UniPro Initialization
              1. 12.3.7.4.1.1.1 UniPro Layer 2 Configuration
                1. 12.3.7.4.1.1.1.1 Layer 2 Threshold Value Calculation
                2. 12.3.7.4.1.1.1.2 DL_TC0TXFCThreshold
                3. 12.3.7.4.1.1.1.3 DL_AFC0CreditThreshold
                4. 12.3.7.4.1.1.1.4 DL_TC0OutAckThreshold
                5. 12.3.7.4.1.1.1.5 Layer 2 Timer Value Calculation
                6. 12.3.7.4.1.1.1.6 DL_FC0ProtectionTimeOutVal
                7. 12.3.7.4.1.1.1.7 DL_TC0ReplayTimeOutVal and DL_AFC0ReqTimeOut
              2. 12.3.7.4.1.1.2 UniPro CPort Connection Management
            2. 12.3.7.4.1.2 UFS Host Controller Initialization
            3. 12.3.7.4.1.3 HCE Bit
          2. 12.3.7.4.2 UFS Host Controller Programming
            1. 12.3.7.4.2.1 UFS Software Model
              1. 12.3.7.4.2.1.1 UFS Layers
              2. 12.3.7.4.2.1.2 UFS Protocol Elements
                1. 12.3.7.4.2.1.2.1 UPIU Types
                2. 12.3.7.4.2.1.2.2 UFS Protocol
              3. 12.3.7.4.2.1.3 UFS Host Data Structure
            2. 12.3.7.4.2.2 UFS Theory Of Operation
              1. 12.3.7.4.2.2.1 Building A UTP Transfer Request
              2. 12.3.7.4.2.2.2 Processing UTP Task Management Request Completion
              3. 12.3.7.4.2.2.3 Building UTP Task Management Request
              4. 12.3.7.4.2.2.4 Processing UTP Transfer Request Completion
              5. 12.3.7.4.2.2.5 UFS Host Processing
              6. 12.3.7.4.2.2.6 UFS Response Management Аnd Command Completion
          3. 12.3.7.4.3 UFS PHY Programming
          4. 12.3.7.4.4 UFS Hibernate Timings Considerations
    4. 12.4  Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
          2. 12.4.1.1.2 ECAP Ports
        2. 12.4.1.2 ECAP Environment
        3. 12.4.1.3 ECAP Functional Description
          1. 12.4.1.3.1 Capture and APWM Operating Modes
            1. 12.4.1.3.1.1 ECAP Capture Mode Description
              1. 12.4.1.3.1.1.1 ECAP Event Prescaler
              2. 12.4.1.3.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.3.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.3.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.3.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.3.1.1.6 ECAP Interrupt Control
              7. 12.4.1.3.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.3.1.2 ECAP APWM Mode Operation
          2. 12.4.1.3.2 Summary of ECAP Functional Registers
        4. 12.4.1.4 ECAP Use Cases
          1. 12.4.1.4.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.4.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.4.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.4.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.4.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.4.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.4.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.4.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.4.5 Application of the APWM Mode
            1. 12.4.1.4.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.4.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.4.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.4.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.4.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.4.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Ports
        2. 12.4.2.2 ECAP Environment
        3. 12.4.2.3 EPWM Functional Description
          1. 12.4.2.3.1  EPWM Submodule Features
            1. 12.4.2.3.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.3.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.3.2.1 Overview
            2. 12.4.2.3.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.2.3.2.3 Calculating PWM Period and Frequency
              1. 12.4.2.3.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.3.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.2.3.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.2.3.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.3.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.3.3.1 Overview
            2. 12.4.2.3.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.3.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.3.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.3.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.3.4.1 Overview
            2. 12.4.2.3.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.3.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.3.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.3.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.3.5.1 Overview
            2. 12.4.2.3.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.3.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.3.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.3.6.1 Overview
            2. 12.4.2.3.6.2 Controlling the EPWM-Chopper Submodule
            3. 12.4.2.3.6.3 Operational Highlights for the EPWM-Chopper Submodule
            4. 12.4.2.3.6.4 EPWM-Chopper Waveforms
              1. 12.4.2.3.6.4.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.3.6.4.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.3.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.3.7.1 Overview
            2. 12.4.2.3.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.3.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.3.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.3.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.3.8.1 Overview
            2. 12.4.2.3.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.3.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.3.8.4 3174
          9. 12.4.2.3.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.3.9.1 Overview
            2. 12.4.2.3.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.3.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.3.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.3.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.3.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.3.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.3.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.3.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.3.11 Proper EPWM Interrupt Initialization Procedure
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Ports
        2. 12.4.3.2 EQEP Environment
        3. 12.4.3.3 EQEP Functional Description
          1. 12.4.3.3.1 EQEP Inputs
          2. 12.4.3.3.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.3.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.3.2.1.1 Quadrature Count Mode
              2. 12.4.3.3.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.3.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.3.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.3.2.2 EQEP Input Polarity Selection
            3. 12.4.3.3.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.3.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.3.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.3.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.3.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.3.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.3.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.3.3.2 EQEP Position Counter Latch
              1. 12.4.3.3.3.2.1 Index Event Latch
              2. 12.4.3.3.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.3.3.3 EQEP Position Counter Initialization
            4. 12.4.3.3.3.4 EQEP Position-Compare Unit
          4. 12.4.3.3.4 EQEP Edge Capture Unit
          5. 12.4.3.3.5 EQEP Watchdog
          6. 12.4.3.3.6 Unit Timer Base
          7. 12.4.3.3.7 EQEP Interrupt Structure
          8. 12.4.3.3.8 Summary of EQEP Functional Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Ports
        2. 12.4.4.2 MCAN Environment
        3. 12.4.4.3 MCAN Functional Description
          1. 12.4.4.3.1  Module Clocking Requirements
          2. 12.4.4.3.2  Interrupt and DMA Requests
            1. 12.4.4.3.2.1 Interrupt Requests
            2. 12.4.4.3.2.2 DMA Requests
          3. 12.4.4.3.3  Operating Modes
            1. 12.4.4.3.3.1 Software Initialization
            2. 12.4.4.3.3.2 Normal Operation
            3. 12.4.4.3.3.3 CAN FD Operation
            4. 12.4.4.3.3.4 Transmitter Delay Compensation
              1. 12.4.4.3.3.4.1 Description
              2. 12.4.4.3.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.3.3.5 Restricted Operation Mode
            6. 12.4.4.3.3.6 Bus Monitoring Mode
            7. 12.4.4.3.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.3.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.3.3.8 Power Down (Sleep Mode)
              1. 12.4.4.3.3.8.1 External Clock Stop Mode
              2. 12.4.4.3.3.8.2 Suspend Mode
              3. 12.4.4.3.3.8.3 Wakeup request
            9. 12.4.4.3.3.9 Test Modes
              1. 12.4.4.3.3.9.1 Internal Loopback Mode
          4. 12.4.4.3.4  Timestamp Generation
            1. 12.4.4.3.4.1 External Timestamp Counter
          5. 12.4.4.3.5  Timeout Counter
          6. 12.4.4.3.6  ECC Support
            1. 12.4.4.3.6.1 ECC Wrapper
            2. 12.4.4.3.6.2 ECC Aggregator
          7. 12.4.4.3.7  Rx Handling
            1. 12.4.4.3.7.1 Acceptance Filtering
              1. 12.4.4.3.7.1.1 Range Filter
              2. 12.4.4.3.7.1.2 Filter for specific IDs
              3. 12.4.4.3.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.3.7.1.4 Standard Message ID Filtering
              5. 12.4.4.3.7.1.5 Extended Message ID Filtering
            2. 12.4.4.3.7.2 Rx FIFOs
              1. 12.4.4.3.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.3.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.3.7.3 Dedicated Rx Buffers
              1. 12.4.4.3.7.3.1 Rx Buffer Handling
            4. 12.4.4.3.7.4 Debug on CAN Support
          8. 12.4.4.3.8  Tx Handling
            1. 12.4.4.3.8.1 Transmit Pause
            2. 12.4.4.3.8.2 Dedicated Tx Buffers
            3. 12.4.4.3.8.3 Tx FIFO
            4. 12.4.4.3.8.4 Tx Queue
            5. 12.4.4.3.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.3.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.3.8.7 Transmit Cancellation
            8. 12.4.4.3.8.8 Tx Event Handling
          9. 12.4.4.3.9  FIFO Acknowledge Handling
          10. 12.4.4.3.10 Message RAM
            1. 12.4.4.3.10.1 Message RAM Configuration
            2. 12.4.4.3.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.3.10.3 Tx Buffer Element
            4. 12.4.4.3.10.4 Tx Event FIFO Element
            5. 12.4.4.3.10.5 Standard Message ID Filter Element
            6. 12.4.4.3.10.6 Extended Message ID Filter Element
    5. 12.5  Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Ports
      2. 12.5.2 Multichannel Audio Serial Port (MCASP)
        1. 12.5.2.1 MCASP Overview
          1. 12.5.2.1.1 MCASP Features
          2. 12.5.2.1.2 MCASP Ports
        2. 12.5.2.2 MCASP Environment
        3. 12.5.2.3 MCASP Functional Description
          1. 12.5.2.3.1  MCASP Block Diagram
          2. 12.5.2.3.2  MCASP Clock and Frame-Sync Configurations
            1. 12.5.2.3.2.1 MCASP Transmit Clock
            2. 12.5.2.3.2.2 MCASP Receive Clock
            3. 12.5.2.3.2.3 Frame-Sync Generator
            4. 12.5.2.3.2.4 Synchronous and Asynchronous Transmit and Receive Operations
          3. 12.5.2.3.3  MCASP Frame Sync Feedback for Cross Synchronization
          4. 12.5.2.3.4  MCASP Serializers
          5. 12.5.2.3.5  MCASP Format Units
            1. 12.5.2.3.5.1 Transmit Format Unit
              1. 12.5.2.3.5.1.1 TDM Mode Transmission Data Alignment Settings
              2. 12.5.2.3.5.1.2 DIT Mode Transmission Data Alignment Settings
            2. 12.5.2.3.5.2 Receive Format Unit
              1. 12.5.2.3.5.2.1 TDM Mode Reception Data Alignment Settings
          6. 12.5.2.3.6  MCASP State-Machines
          7. 12.5.2.3.7  MCASP TDM Sequencers
          8. 12.5.2.3.8  MCASP Software Reset
          9. 12.5.2.3.9  MCASP Power Management
          10. 12.5.2.3.10 MCASP Transfer Modes
            1. 12.5.2.3.10.1 Burst Transfer Mode
            2. 12.5.2.3.10.2 Time-Division Multiplexed (TDM) Transfer Mode
              1. 12.5.2.3.10.2.1 TDM Time Slots Generation and Processing
              2. 12.5.2.3.10.2.2 Special 384-Slot TDM Mode for Connection to External DIR
            3. 12.5.2.3.10.3 DIT Transfer Mode
              1. 12.5.2.3.10.3.1 Transmit DIT Encoding
              2. 12.5.2.3.10.3.2 Transmit DIT Clock and Frame-Sync Generation
              3. 12.5.2.3.10.3.3 DIT Channel Status and User Data Register Files
          11. 12.5.2.3.11 MCASP Data Transmission and Reception
            1. 12.5.2.3.11.1 Data Ready Status and Event/Interrupt Generation
              1. 12.5.2.3.11.1.1 Transmit Data Ready
              2. 12.5.2.3.11.1.2 Receive Data Ready
              3. 12.5.2.3.11.1.3 Transfers Through the Data Port (DATA)
              4. 12.5.2.3.11.1.4 Transfers Through the Configuration Bus (CFG)
              5. 12.5.2.3.11.1.5 Using a Device CPU for MCASP Servicing
              6. 12.5.2.3.11.1.6 Using the DMA for MCASP Servicing
          12. 12.5.2.3.12 MCASP Audio FIFO (AFIFO)
            1. 12.5.2.3.12.1 AFIFO Data Transmission
              1. 12.5.2.3.12.1.1 Transmit DMA Event Pacer
            2. 12.5.2.3.12.2 AFIFO Data Reception
              1. 12.5.2.3.12.2.1 Receive DMA Event Pacer
            3. 12.5.2.3.12.3 Arbitration Between Transmit and Receive DMA Requests
          13. 12.5.2.3.13 MCASP Events and Interrupt Requests
            1. 12.5.2.3.13.1 Transmit Data Ready Event and Interrupt
            2. 12.5.2.3.13.2 Receive Data Ready Event and Interrupt
            3. 12.5.2.3.13.3 Error Interrupt
            4. 12.5.2.3.13.4 Multiple Interrupts
          14. 12.5.2.3.14 MCASP DMA Requests
          15. 12.5.2.3.15 MCASP Loopback Modes
            1. 12.5.2.3.15.1 Loopback Mode Configurations
          16. 12.5.2.3.16 MCASP Error Reporting
            1. 12.5.2.3.16.1 Buffer Underrun Error -Transmitter
            2. 12.5.2.3.16.2 Buffer Overrun Error-Receiver
            3. 12.5.2.3.16.3 DATA Port Error - Transmitter
            4. 12.5.2.3.16.4 DATA Port Error - Receiver
            5. 12.5.2.3.16.5 Unexpected Frame Sync Error
            6. 12.5.2.3.16.6 Clock Failure Detection
              1. 12.5.2.3.16.6.1 Clock Failure Check Startup
              2. 12.5.2.3.16.6.2 Transmit Clock Failure Check and Recovery
              3. 12.5.2.3.16.6.3 Receive Clock Failure Check and Recovery
        4. 12.5.2.4 MCASP Programming Guide
          1. 12.5.2.4.1 MCASP Operational Modes Configuration
            1. 12.5.2.4.1.1 MCASP Transmission Modes
              1. 12.5.2.4.1.1.1 Main Sequence – MCASP DIT- /TDM- Polling Transmission Method
              2. 12.5.2.4.1.1.2 Main Sequence – MCASP DIT- /TDM - Interrupt Transmission Method
              3. 12.5.2.4.1.1.3 Main Sequence –MCASP DIT- /TDM - Mode DMA Transmission Method
            2. 12.5.2.4.1.2 MCASP Reception Modes
              1. 12.5.2.4.1.2.1 Main Sequence – MCASP Polling Reception Method
              2. 12.5.2.4.1.2.2 Main Sequence – MCASP TDM - Interrupt Reception Method
              3. 12.5.2.4.1.2.3 Main Sequence – MCASP TDM - Mode DMA Reception Method
            3. 12.5.2.4.1.3 MCASP Event Servicing
              1. 12.5.2.4.1.3.1 MCASP DIT-/TDM- Transmit Interrupt Events Servicing
              2. 12.5.2.4.1.3.2 MCASP TDM- Receive Interrupt Events Servicing
              3. 12.5.2.4.1.3.3 Subsequence – MCASP DIT-/TDM -Modes Transmit Error Handling
              4. 12.5.2.4.1.3.4 Subsequence – MCASP Receive Error Handling
    6. 12.6  Display Subsystem (DSS) and Peripherals
      1. 12.6.1 DSS Overview
        1. 12.6.1.1 DSS Features
        2. 12.6.1.2 DSS Ports
      2. 12.6.2 DSS Environment
      3. 12.6.3 Display Subsystem Controller (DISPC) with Frame Buffer Decompression Core (FBDC)
        1. 12.6.3.1  DISPC Overview
        2. 12.6.3.2  DISPC Clocks
        3. 12.6.3.3  DISPC Resets
        4. 12.6.3.4  DISPC Power Management
        5. 12.6.3.5  DISPC Interrupt Requests
        6. 12.6.3.6  DISPC DMA Controller
          1. 12.6.3.6.1  DISPC DMA Addressing and Bursts
          2. 12.6.3.6.2  DISPC Read DMA Buffers
          3. 12.6.3.6.3  DISPC Write DMA Buffer
          4. 12.6.3.6.4  DISPC Flip/Mirror Support
          5. 12.6.3.6.5  DISPC DMA Predecimation
          6. 12.6.3.6.6  DISPC DMA Buffer Sharing
          7. 12.6.3.6.7  DISPC DMA MFLAG Mechanism
          8. 12.6.3.6.8  DISPC DMA Priority Requests Control
          9. 12.6.3.6.9  DISPC DMA Arbitration
          10. 12.6.3.6.10 DISPC DMA Ultra-Low Power Mode
          11. 12.6.3.6.11 DISPC Compressed Data Format Support
            1. 12.6.3.6.11.1 FBDC Tile Request
            2. 12.6.3.6.11.2 FBDC Source Cropping
        7. 12.6.3.7  DISPC Pixel Data Formats
        8. 12.6.3.8  DISPC Video Pipeline
          1. 12.6.3.8.1 DISPC VID Replication Logic
          2. 12.6.3.8.2 DISPC VID VC-1 Range Mapping Unit
          3. 12.6.3.8.3 DISPC VID Color Look-Up Table (CLUT)
          4. 12.6.3.8.4 DISPC VID Chrominance Resampling
            1. 12.6.3.8.4.1 Chrominance Resampling for VID Pipeline
            2. 12.6.3.8.4.2 Chrominance Resampling for VIDL Pipeline
          5. 12.6.3.8.5 DISPC VID Scaler Unit
          6. 12.6.3.8.6 DISPC VID Color Space Conversion YUV to RGB
          7. 12.6.3.8.7 DISPC VID Brightness/Contrast/Saturation/Hue Control
          8. 12.6.3.8.8 DISPC VID Luma Key Support
          9. 12.6.3.8.9 DISPC VID Cropping Support
        9. 12.6.3.9  DISPC Write-Back Pipeline
          1. 12.6.3.9.1 DISPC WB Color Space Conversion RGB to YUV
          2. 12.6.3.9.2 DISPC WB Scaler Unit
        10. 12.6.3.10 DISPC Overlay Manager
          1. 12.6.3.10.1 DISPC Overlay Input Selector
          2. 12.6.3.10.2 DISPC Overlay Mechanism
            1. 12.6.3.10.2.1 Overlay Alpha Blender
            2. 12.6.3.10.2.2 Overlay Transparency Color Keys
          3. 12.6.3.10.3 Overlay 3D Support
          4. 12.6.3.10.4 Overlay Color Bar Insertion
        11. 12.6.3.11 DISPC Video Port Output
          1. 12.6.3.11.1 DISPC VP Gamma Correction Unit
          2. 12.6.3.11.2 DISPC VP Color Phase Rotation Unit
          3. 12.6.3.11.3 DISPC VP Color Space Conversion - RGB to YUV
          4. 12.6.3.11.4 DISPC VP BT.656 and BT.1120 Modes
            1. 12.6.3.11.4.1 DISPC BT Mode Blanking
            2. 12.6.3.11.4.2 DISPC BT Mode EAV and SAV
          5. 12.6.3.11.5 DISPC VP Spatial/Temporal Dithering
          6. 12.6.3.11.6 DISPC VP Multiple Cycle Output Format (TDM)
          7. 12.6.3.11.7 DISPC VP Stall Mode
          8. 12.6.3.11.8 DISPC VP Timing Generator and Display Panel Settings
          9. 12.6.3.11.9 DISPC VP Merge-Split-Sync (MSS) Module
            1. 12.6.3.11.9.1 MSS Clocking Scheme
            2. 12.6.3.11.9.2 MSS Merge with Scaling
        12. 12.6.3.12 DISPC Internal Diagnostic Features
          1. 12.6.3.12.1 Internal Diagnostic Check Regions
          2. 12.6.3.12.2 Internal Diagnostic Signature Generator Using MISR
          3. 12.6.3.12.3 Internal Diagnostic Checks
          4. 12.6.3.12.4 Internal Diagnostic Check Limitations
        13. 12.6.3.13 DISPC Security Management
          1. 12.6.3.13.1 Security Implementation
          2. 12.6.3.13.2 Secure Mode Configuration
        14. 12.6.3.14 DISPC Resources Sharing
          1. 12.6.3.14.1 Register Region per Sub-component
          2. 12.6.3.14.2 Interrupt Duplication
          3. 12.6.3.14.3 Independent Context Update for Pipelines
          4. 12.6.3.14.4 CHANNELID Support
        15. 12.6.3.15 DISPC Shadow Mechanism for Registers
      4. 12.6.4 MIPI Display Serial Interface (DSI) Controller
        1. 12.6.4.1 DSI Block Diagram
        2. 12.6.4.2 DSI Clocking
        3. 12.6.4.3 DSI Reset
        4. 12.6.4.4 DSI Power Management
        5. 12.6.4.5 DSI Interrupts
        6. 12.6.4.6 DSI Internal Interfaces
          1. 12.6.4.6.1 Video Input Interfaces
            1. 12.6.4.6.1.1 Pixel Mapping
          2. 12.6.4.6.2 DPI (Pixel Stream Interface)
            1. 12.6.4.6.2.1 Signals
          3. 12.6.4.6.3 SDI (Serial Data Interface)
            1. 12.6.4.6.3.1 Secure Display Support
        7. 12.6.4.7 DSI Programming Guide
          1. 12.6.4.7.1  Application Guidelines
            1. 12.6.4.7.1.1 Overview of a Display Subsystem
            2. 12.6.4.7.1.2 D-PHY And DSI Configuration
            3. 12.6.4.7.1.3 DSI Controller Initialization
            4. 12.6.4.7.1.4 Panel Configuration Using Command Mode
            5. 12.6.4.7.1.5 VIDEO Interface Configuration
          2. 12.6.4.7.2  Application Considerations
            1. 12.6.4.7.2.1 D-PHY Timings Control
            2. 12.6.4.7.2.2 Control Block
            3. 12.6.4.7.2.3 Video Coherency
          3. 12.6.4.7.3  Start-up Procedure
          4. 12.6.4.7.4  Interrupt Management
            1. 12.6.4.7.4.1 Error and Status Registers
            2. 12.6.4.7.4.2 Interrupt Management for Direct Command Registers
          5. 12.6.4.7.5  Direct Command Usage
            1. 12.6.4.7.5.1 Trigger Mapping Information
            2. 12.6.4.7.5.2 Command Mode Settings
            3. 12.6.4.7.5.3 Bus Turnaround Sequence
            4. 12.6.4.7.5.4 Tearing Effect Control
            5. 12.6.4.7.5.5 Tearing Effect Control on Panels with Frame Buffer
            6. 12.6.4.7.5.6 Return Path Operation
            7. 12.6.4.7.5.7 EoT Packet Management
            8. 12.6.4.7.5.8 ECC Correction
            9. 12.6.4.7.5.9 LP Transmission and BTA
          6. 12.6.4.7.6  Low-power Management
          7. 12.6.4.7.7  Video Mode Settings
            1. 12.6.4.7.7.1 Video Stream Presentation
            2. 12.6.4.7.7.2 Video Stream Settings (VSG)
            3. 12.6.4.7.7.3 VCA Configuration
            4. 12.6.4.7.7.4 TVG Configuration
          8. 12.6.4.7.8  DPI To DSI Programming
            1. 12.6.4.7.8.1 DSI and DPHY Operation
            2. 12.6.4.7.8.2 Pixel Clock to TX_BYTE_CLK Variation
            3. 12.6.4.7.8.3 LP Operation
            4. 12.6.4.7.8.4 DPI Interface Burst Operation
          9. 12.6.4.7.9  Programming the DSITX Controller to Match the Incoming DPI Stream
            1. 12.6.4.7.9.1 Vertical Timing
            2. 12.6.4.7.9.2 Horizontal Timing for Non-Burst Mode with Sync Pulses
            3. 12.6.4.7.9.3 Event Mode Horizontal Timing
            4. 12.6.4.7.9.4 Burst Event Mode Horizontal Timing
            5. 12.6.4.7.9.5 Burst Mode Operation
            6. 12.6.4.7.9.6 Example Configurations
            7. 12.6.4.7.9.7 Stereoscopic Video Support
          10. 12.6.4.7.10 DSITX Video Stream Variable Refresh
      5. 12.6.5 Embedded DisplayPort (еDP) Transmitter
        1. 12.6.5.1 EDP Block Diagram
        2. 12.6.5.2 EDP Wrapper Functions
          1. 12.6.5.2.1 Video Stream Clock/Data Muxing
          2. 12.6.5.2.2 Secure Video Content Protection
          3. 12.6.5.2.3 DPI_DATA Input Pixel Format Supported
          4. 12.6.5.2.4 Audio Input Interface
            1. 12.6.5.2.4.1 Audio I2S Signals/Timing
            2. 12.6.5.2.4.2 Audio I2S Clock Frequency
        3. 12.6.5.3 EDP Transmitter Controller Subsystem (MHDPTX_TOP)
          1. 12.6.5.3.1 Display Stream Compression Encoder (DSC)
            1. 12.6.5.3.1.1 DSC Encoder Features
            2. 12.6.5.3.1.2 Usage Models for EDP
          2. 12.6.5.3.2 Display Port Transmitter Controller (MHDPTX Controller)
            1. 12.6.5.3.2.1 EDP Transmitter Controller Mode Configurations
        4. 12.6.5.4 EDP AUX_PHY Interface
        5. 12.6.5.5 EDP Clocks
          1. 12.6.5.5.1 Clock Diagram
            1. 12.6.5.5.1.1 DPI Interface Clock Sourcing
            2. 12.6.5.5.1.2 Memory Clock Gating
            3. 12.6.5.5.1.3 PHY Clock Connections
          2. 12.6.5.5.2 Clock Groups
        6. 12.6.5.6 EDP Resets
        7. 12.6.5.7 EDP Interrupt Requests
          1. 12.6.5.7.1 EDP_INTR Interrupt Description
          2. 12.6.5.7.2 EDP_INTR_ASF Interrupt Description
        8. 12.6.5.8 EDP Embedded Memories
          1. 12.6.5.8.1 MHDPTX Controller Memories
          2. 12.6.5.8.2 DSC Memories
          3. 12.6.5.8.3 ECC Aggregation
        9. 12.6.5.9 EDP Programmer's Guide
          1. 12.6.5.9.1 EDP Controller Programming
            1. 12.6.5.9.1.1  MHDPTX Register/Memory Regions
            2. 12.6.5.9.1.2  Boot Sequence
            3. 12.6.5.9.1.3  Setting Core Clock Frequency
            4. 12.6.5.9.1.4  Loading Firmware
            5. 12.6.5.9.1.5  FW Running indication
            6. 12.6.5.9.1.6  Software Events Handling
            7. 12.6.5.9.1.7  DisplayPort Source (TX) Sequence
            8. 12.6.5.9.1.8  HDCP
              1. 12.6.5.9.1.8.1 Embedded HDCP Crypto
              2. 12.6.5.9.1.8.2 Additional Security Features
                1. 12.6.5.9.1.8.2.1 KM-Key Encryption
                2. 12.6.5.9.1.8.2.2 Cyphertext Stealing
            9. 12.6.5.9.1.9  HD Display TX Controller
              1. 12.6.5.9.1.9.1 Info-Frame Handling
                1. 12.6.5.9.1.9.1.1 EDID Handling
                2. 12.6.5.9.1.9.1.2 Audio Control
                3. 12.6.5.9.1.9.1.3 Video Control
            10. 12.6.5.9.1.10 DPTX TX Controller
              1. 12.6.5.9.1.10.1 Protocol over Auxiliary
              2. 12.6.5.9.1.10.2 PHY (Physical layer) Handling
          2. 12.6.5.9.2 EDP PHY Wrapper Initialization
          3. 12.6.5.9.3 EDP PHY Programming
    7. 12.7  Camera Subsystem
      1. 12.7.1 Camera Streaming Interface Receiver (CSI_RX_IF)
        1. 12.7.1.1 CSI_RX_IF Overview
          1. 12.7.1.1.1 CSI_RX_IF Features
          2. 12.7.1.1.2 CSI_RX_IF Ports
        2. 12.7.1.2 CSI_RX_IF Environment
        3. 12.7.1.3 CSI_RX_IF Functional Description
          1. 12.7.1.3.1 CSI_RX_IF Block Diagram
          2. 12.7.1.3.2 CSI_RX_IF Hardware and Software Reset
          3. 12.7.1.3.3 CSI_RX_IF Clock Configuration
          4. 12.7.1.3.4 CSI_RX_IF Interrupt Events
          5. 12.7.1.3.5 CSI_RX_IF Data Memory Organization Details
          6. 12.7.1.3.6 CSI_RX_IF PSI_L (DMA) Interface
            1. 12.7.1.3.6.1 PSI_L DMA framing
            2. 12.7.1.3.6.2 PSI_L DMA error handling due to FIFO overflow
          7. 12.7.1.3.7 CSI_RX_IF ECC Protection Support
          8. 12.7.1.3.8 CSI_RX_IF Programming Guide
            1. 12.7.1.3.8.1  Overview
            2. 12.7.1.3.8.2  Controller Configuration
            3. 12.7.1.3.8.3  Power on Configuration
            4. 12.7.1.3.8.4  Stream Start and Stop
            5. 12.7.1.3.8.5  Error Control With Soft Resets
            6. 12.7.1.3.8.6  Stream Error Detected – No Error Bypass Mode
            7. 12.7.1.3.8.7  Stream Error Detected – Error Bypass Mode
            8. 12.7.1.3.8.8  Stream Error Detected – Soft Reset Recovery
            9. 12.7.1.3.8.9  Stream Monitor Configuration
            10. 12.7.1.3.8.10 Stream Monitor Frame Capture Control
            11. 12.7.1.3.8.11 Stream Monitor Timer interrupt
            12. 12.7.1.3.8.12 Stream Monitor Line/Byte Counters Interrupt
            13. 12.7.1.3.8.13 Example Controller Programming Sequence (Single Stream Operation)
            14. 12.7.1.3.8.14 CSI_RX_IF Programming Restrictions
            15. 12.7.1.3.8.15 CSI_RX_IF Real-time operating requirements
      2. 12.7.2 MIPI D-PHY Receiver (DPHY_RX)
        1. 12.7.2.1 DPHY_RX Overview
          1. 12.7.2.1.1 DPHY_RX Features
          2. 12.7.2.1.2 DPHY_RX Ports
            1. 12.7.2.1.2.1 DPHY_RX Integration in MAIN Domain
        2. 12.7.2.2 DPHY_RX Environment
        3. 12.7.2.3 DPHY_RX Functional Description
          1. 12.7.2.3.1 DPHY_RX Programming Guide
            1. 12.7.2.3.1.1 Overview
            2. 12.7.2.3.1.2 Initial Configuration Programming
              1. 12.7.2.3.1.2.1 Start-up Sequence Timing Diagram
            3. 12.7.2.3.1.3 Common Configuration
            4. 12.7.2.3.1.4 Lane Configuration
            5. 12.7.2.3.1.5 Procedure: Clock Lane Low Power Analog Receiver Functions Test
              1. 12.7.2.3.1.5.1 Description of Procedure
              2. 12.7.2.3.1.5.2 Details of the Procedure
            6. 12.7.2.3.1.6 Procedure: Data Lane Low Power Analog Receiver Functions Test
              1. 12.7.2.3.1.6.1 Description of Procedure
              2. 12.7.2.3.1.6.2 Details of the Procedure
            7. 12.7.2.3.1.7 Procedure: Clock and Data Lane High Speed Receiver BIST Functions Test
              1. 12.7.2.3.1.7.1 Description of Procedure
              2. 12.7.2.3.1.7.2 Details of the Procedure
      3. 12.7.3 Camera Streaming Interface Transmitter (CSI_TX_IF)
        1. 12.7.3.1 CSI_TX_IF Overview
          1. 12.7.3.1.1 CSI_TX_IF Ports
        2. 12.7.3.2 CSI_TX_IF Features
          1. 12.7.3.2.1 CSI_TX_IF Legacy Compatibility
        3. 12.7.3.3 CSI_TX_IF Environment
        4. 12.7.3.4 CSI_TX_IF Functional Description
          1. 12.7.3.4.1 CSI_TX_IF Block Diagram
          2. 12.7.3.4.2 CSI_TX_IF Hardware and Software Reset
          3. 12.7.3.4.3 CSI_TX_IF Clock Configuration
          4. 12.7.3.4.4 CSI_TX_IF Interrupt Events
          5. 12.7.3.4.5 CSI_TX_IF Data Memory Organization Details
          6. 12.7.3.4.6 CSI_TX_IF PSI_L (DMA) Interface
          7. 12.7.3.4.7 CSI_TX_IF ECC Protection Support
        5. 12.7.3.5 CSI_TX_IF Programming Guide
          1. 12.7.3.5.1  CSI_TX_IF Programming (Configuration Mode)
          2. 12.7.3.5.2  CSI_TX_IF System Initialization Programming
          3. 12.7.3.5.3  CSI_TX_IF Lane Control Programming
          4. 12.7.3.5.4  CSI_TX_IF Virtual Channel and Data Type Management
            1. 12.7.3.5.4.1 CSI_TX_IF Data Type Interleaving
            2. 12.7.3.5.4.2 CSI_TX_IF Data Type Interleaving with Multiple Interfaces
            3. 12.7.3.5.4.3 CSI_TX_IF Virtual Channel Interleaving
            4. 12.7.3.5.4.4 CSI_TX_IF Virtual Channel and Data Type Interleaving
          5. 12.7.3.5.5  CSI_TX_IF Line Control
            1. 12.7.3.5.5.1 CSI_TX_IF Line Control Arbitration
          6. 12.7.3.5.6  CSI_TX_IF Lane Manager FSM
          7. 12.7.3.5.7  CSI_TX_IF Data Lane Control FSM
          8. 12.7.3.5.8  CSI_TX_IF Application Examples
            1. 12.7.3.5.8.1 CSI_TX_IF D-PHY Control and Configuration
            2. 12.7.3.5.8.2 CSI_TX_IF Clock and Data Lane Enable
            3. 12.7.3.5.8.3 CSI_TX_IF DP/DN Signal Swap
          9. 12.7.3.5.9  CSI_TX_IF DPHY_TX Status
          10. 12.7.3.5.10 CSI_TX_IF ULPS Operation
          11. 12.7.3.5.11 CSI_TX_IF System Frame Rate Measurement
          12. 12.7.3.5.12 CSI_TX_IF Configuration for PSI_L
          13. 12.7.3.5.13 CSI_TX_IF Configuration for Color Bar
          14. 12.7.3.5.14 CSI_TX_IF Error Recovery
          15. 12.7.3.5.15 CSI_TX_IF Power up/down Sequence
    8. 12.8  Shared MIPI D-PHY Transmitter (DPHY_TX)
      1. 12.8.1 DPHY_TX Subsystem Overview
        1. 12.8.1.1 DPHY_TX Features
        2. 12.8.1.2 DPHY_TX Ports
      2. 12.8.2 DPHY_TX Environment
    9. 12.9  Timer Modules
      1. 12.9.1 Global Timebase Counter (GTC)
        1. 12.9.1.1 GTC Overview
          1. 12.9.1.1.1 GTC Features
          2. 12.9.1.1.2 GTC Ports
        2. 12.9.1.2 GTC Functional Description
          1. 12.9.1.2.1 GTC Block Diagram
          2. 12.9.1.2.2 GTC Counter
          3. 12.9.1.2.3 GTC Gray Encoder
          4. 12.9.1.2.4 GTC Push Event Generation
          5. 12.9.1.2.5 GTC Register Partitioning
      2. 12.9.2 Windowed Watchdog Timer (WWDT)
        1. 12.9.2.1 RTI Overview
          1. 12.9.2.1.1 RTI Features
          2. 12.9.2.1.2 RTI Ports
        2. 12.9.2.2 RTI Functional Description
          1. 12.9.2.2.1 RTI Counter Operation
          2. 12.9.2.2.2 RTI Digital Watchdog
          3. 12.9.2.2.3 RTI Digital Windowed Watchdog
          4. 12.9.2.2.4 RTI Low Power Mode Operation
          5. 12.9.2.2.5 RTI Debug Mode Behavior
      3. 12.9.3 Timers
        1. 12.9.3.1 Timers Overview
          1. 12.9.3.1.1 Timers Features
          2. 12.9.3.1.2 Timers Ports
        2. 12.9.3.2 Timers Environment
        3. 12.9.3.3 Timers Functional Description
          1. 12.9.3.3.1  Timer Block Diagram
          2. 12.9.3.3.2  Timer Power Management
            1. 12.9.3.3.2.1 Wake-Up Capability
          3. 12.9.3.3.3  Timer Software Reset
          4. 12.9.3.3.4  Timer Interrupts
          5. 12.9.3.3.5  Timer Mode Functionality
            1. 12.9.3.3.5.1 1-ms Tick Generation
          6. 12.9.3.3.6  Timer Capture Mode Functionality
          7. 12.9.3.3.7  Timer Compare Mode Functionality
          8. 12.9.3.3.8  Timer Prescaler Functionality
          9. 12.9.3.3.9  Timer Pulse-Width Modulation
          10. 12.9.3.3.10 Timer Counting Rate
          11. 12.9.3.3.11 Timer Under Emulation
          12. 12.9.3.3.12 Accessing Timer Registers
            1. 12.9.3.3.12.1 Writing to Timer Registers
              1. 12.9.3.3.12.1.1 Write Posting Synchronization Mode
              2. 12.9.3.3.12.1.2 Write Nonposting Synchronization Mode
            2. 12.9.3.3.12.2 Reading From Timer Counter Registers
              1. 12.9.3.3.12.2.1 Read Posted
              2. 12.9.3.3.12.2.2 Read Non-Posted
          13. 12.9.3.3.13 Timer Posted Mode Selection
        4. 12.9.3.4 Timers Low-Level Programming Models
          1. 12.9.3.4.1 Timer Operational Mode Configuration
            1. 12.9.3.4.1.1 Timer Mode
              1. 12.9.3.4.1.1.1 Main Sequence – Timer Mode Configuration
            2. 12.9.3.4.1.2 Timer Compare Mode
              1. 12.9.3.4.1.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.9.3.4.1.3 Timer Capture Mode
              1. 12.9.3.4.1.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.9.3.4.1.3.2 Subsequence – Initialize Capture Mode
              3. 12.9.3.4.1.3.3 Subsequence – Detect Event
            4. 12.9.3.4.1.4 Timer PWM Mode
              1. 12.9.3.4.1.4.1 Main Sequence – Timer PWM Mode Configuration
    10. 12.10 Internal Diagnostics Modules
      1. 12.10.1 Dual Clock Comparator (DCC)
        1. 12.10.1.1 DCC Overview
          1. 12.10.1.1.1 DCC Features
          2. 12.10.1.1.2 DCC Ports
        2. 12.10.1.2 DCC Functional Description
          1. 12.10.1.2.1 DCC Counter Operation
          2. 12.10.1.2.2 DCC Low Power Mode Operation
          3. 12.10.1.2.3 DCC Suspend Mode Behavior
          4. 12.10.1.2.4 DCC Single-Shot Mode
          5. 12.10.1.2.5 DCC Continuous mode
            1. 12.10.1.2.5.1 DCC Continue on Error
            2. 12.10.1.2.5.2 DCC Error Count
          6. 12.10.1.2.6 DCC Control and count hand-off across clock domains
          7. 12.10.1.2.7 DCC Error Trajectory record
            1. 12.10.1.2.7.1 DCC FIFO capturing for Errors
            2. 12.10.1.2.7.2 DCC FIFO in continuous capture mode
            3. 12.10.1.2.7.3 DCC FIFO Details
            4. 12.10.1.2.7.4 DCC FIFO Debug mode behavior
          8. 12.10.1.2.8 DCC Count read registers
      2. 12.10.2 Error Signaling Module (ESM)
        1. 12.10.2.1 ESM Overview
          1. 12.10.2.1.1 ESM Features
          2. 12.10.2.1.2 ESM Ports
        2. 12.10.2.2 ESM Environment
        3. 12.10.2.3 ESM Functional Description
          1. 12.10.2.3.1 ESM Interrupt Requests
            1. 12.10.2.3.1.1 ESM Configuration Error Interrupt
            2. 12.10.2.3.1.2 ESM Low Priority Error Interrupt
              1. 12.10.2.3.1.2.1 ESM Low Priority Error Level Event
              2. 12.10.2.3.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.10.2.3.1.3 ESM High Priority Error Interrupt
              1. 12.10.2.3.1.3.1 ESM High Priority Error Level Event
              2. 12.10.2.3.1.3.2 ESM High Priority Error Pulse Event
          2. 12.10.2.3.2 ESM Error Event Inputs
          3. 12.10.2.3.3 ESM Error Pin Output
          4. 12.10.2.3.4 PWM Mode
          5. 12.10.2.3.5 ESM Minimum Time Interval
          6. 12.10.2.3.6 ESM Protection for Registers
          7. 12.10.2.3.7 ESM Clock Stop
      3. 12.10.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.10.3.1 MCRC Overview
          1. 12.10.3.1.1 MCRC Features
          2. 12.10.3.1.2 MCRC Ports
        2. 12.10.3.2 MCRC Functional Description
          1. 12.10.3.2.1  MCRC Block Diagram
          2. 12.10.3.2.2  MCRC General Operation
          3. 12.10.3.2.3  MCRC Modes of Operation
            1. 12.10.3.2.3.1 AUTO Mode
            2. 12.10.3.2.3.2 Semi-CPU Mode
            3. 12.10.3.2.3.3 Full-CPU Mode
          4. 12.10.3.2.4  PSA Signature Register
          5. 12.10.3.2.5  PSA Sector Signature Register
          6. 12.10.3.2.6  CRC Value Register
          7. 12.10.3.2.7  Raw Data Register
          8. 12.10.3.2.8  Example DMA Controller Setup
            1. 12.10.3.2.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.10.3.2.8.2 AUTO Mode Using Software Trigger
            3. 12.10.3.2.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.10.3.2.9  Pattern Count Register
          10. 12.10.3.2.10 Sector Count Register/Current Sector Register
          11. 12.10.3.2.11 Interrupts
            1. 12.10.3.2.11.1 Compression Complete Interrupt
            2. 12.10.3.2.11.2 CRC Fail Interrupt
            3. 12.10.3.2.11.3 Overrun Interrupt
            4. 12.10.3.2.11.4 Underrun Interrupt
            5. 12.10.3.2.11.5 Timeout Interrupt
            6. 12.10.3.2.11.6 Interrupt Offset Register
            7. 12.10.3.2.11.7 Error Handling
          12. 12.10.3.2.12 Power Down Mode
          13. 12.10.3.2.13 Emulation
        3. 12.10.3.3 MCRC Programming Examples
          1. 12.10.3.3.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.10.3.3.1.1 DMA Setup
            2. 12.10.3.3.1.2 Timer Setup
            3. 12.10.3.3.1.3 CRC Setup
          2. 12.10.3.3.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.10.3.3.2.1 DMA Setup
            2. 12.10.3.3.2.2 CRC Setup
          3. 12.10.3.3.3 Example: Semi-CPU Mode
            1. 12.10.3.3.3.1 DMA Setup
            2. 12.10.3.3.3.2 Timer Setup
            3. 12.10.3.3.3.3 CRC Setup
          4. 12.10.3.3.4 Example: Full-CPU Mode
            1. 12.10.3.3.4.1 CRC Setup
      4. 12.10.4 ECC Aggregator
        1. 12.10.4.1 ECC Aggregator Overview
          1. 12.10.4.1.1 ECC Aggregator Features
          2. 12.10.4.1.2 ECC Aggregator Ports
        2. 12.10.4.2 ECC Aggregator Functional Description
          1. 12.10.4.2.1 ECC Aggregator Block Diagram
          2. 12.10.4.2.2 ECC Aggregator Register Groups
          3. 12.10.4.2.3 Read Access to the ECC Control and Status Registers
          4. 12.10.4.2.4 Serial Write Operation
          5. 12.10.4.2.5 Interrupts
          6. 12.10.4.2.6 Inject Only Mode
        3. 12.10.4.3 ECC Aggregator Configurations
          1.        3807
          2.        3808
          3.        3809
          4.        3810
          5.        3811
          6.        3812
          7.        3813
          8.        3814
          9.        3815
          10.        3816
          11.        3817
          12.        3818
          13.        3819
          14.        3820
          15.        3821
          16.        3822
          17.        3823
          18.        3824
          19.        3825
          20.        3826
          21.        3827
          22.        3828
          23.        3829
          24.        3830
          25.        3831
          26.        3832
          27.        3833
          28.        3834
          29.        3835
          30.        3836
          31.        3837
          32.        3838
          33.        3839
          34.        3840
          35.        3841
          36.        3842
          37.        3843
          38.        3844
          39.        3845
          40.        3846
          41.        3847
          42.        3848
          43.        3849
          44.        3850
          45.        3851
          46.        3852
          47.        3853
          48.        3854
          49.        3855
          50.        3856
          51.        3857
          52.        3858
          53.        3859
          54.        3860
          55.        3861
          56.        3862
          57.        3863
          58.        3864
          59.        3865
          60.        3866
          61.        3867
          62.        3868
          63.        3869
          64.        3870
          65.        3871
          66.        3872
          67.        3873
          68.        3874
          69.        3875
          70.        3876
          71.        3877
          72.        3878
          73.        3879
          74.        3880
          75.        3881
          76.        3882
          77.        3883
          78.        3884
          79.        3885
          80.        3886
          81.        3887
          82.        3888
          83.        3889
          84.        3890
          85.        3891
          86.        3892
          87.        3893
          88.        3894
          89.        3895
          90.        3896
          91.        3897
          92.        3898
          93.        3899
          94.        3900
          95.        3901
          96.        3902
          97.        3903
          98.        3904
          99.        3905
          100.        3906
          101.        3907
          102.        3908
          103.        3909
          104.        3910
          105.        3911
          106.        3912
        4. 12.10.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
    1. 13.1 Introduction to SoC Debug Framework
    2. 13.2 Debug Interfaces
      1. 13.2.1 JTAG Interface
      2. 13.2.2 Trace Port
      3. 13.2.3 Trace Connector and Board Layout Considerations
    3. 13.3 SoC Level Debug
      1. 13.3.1  Debug Subsystem
      2. 13.3.2  Debug Cells
        1. 13.3.2.1 Debug Cell Features
          1. 13.3.2.1.1 MCU_DEBUGCELL Features
          2. 13.3.2.1.2 SOC_DEBUGCELL Features
          3. 13.3.2.1.3 CC_DEBUGCELL Features
      3. 13.3.3  Trace Infrastructure
        1. 13.3.3.1 Trace Data Flow
        2. 13.3.3.2 Trace Export Paths
        3. 13.3.3.3 ATB Slave Port Mapping
          1. 13.3.3.3.1 DEBUGSS ATB Mapping
          2. 13.3.3.3.2 CC_DEBUGCELL ATB Mapping
          3. 13.3.3.3.3 SOC_DEBUGCELL ATB Mapping
          4. 13.3.3.3.4 MCU_DEBUGCELL ATB Mapping
      4. 13.3.4  Debug and Interconnect Visibility
        1. 13.3.4.1 SoC Level Probes
          1. 13.3.4.1.1 Latency Statistics Collection
          2. 13.3.4.1.2 Throughput Statistics Collection
          3. 13.3.4.1.3 Transaction Trace Capture
          4. 13.3.4.1.4 Probe Filtering
          5. 13.3.4.1.5 Probe Cross Trigger Support
          6. 13.3.4.1.6 Probe Ownership
        2. 13.3.4.2 Trace Aggregators
          1. 13.3.4.2.1 Trace Input Bus Interface
          2. 13.3.4.2.2 Message Management
            1. 13.3.4.2.2.1 HLTM Format
            2. 13.3.4.2.2.2 Data Payload
            3. 13.3.4.2.2.3 Time Reconstruction
          3. 13.3.4.2.3 Trace Aggregator Ownership
        3. 13.3.4.3 Trace Source Mapping to Trace Aggregator Inputs
      5. 13.3.5  Software Message Trace
        1. 13.3.5.1 STM Features
        2. 13.3.5.2 STM Master ID Mapping
      6. 13.3.6  Hardware Event Trace and Profiling
        1. 13.3.6.1 CTSET Features
        2. 13.3.6.2 CTSET Message Protocol
          1. 13.3.6.2.1 Counter Configuration Message
          2. 13.3.6.2.2 Counter State Message
        3. 13.3.6.3 SoC Level Event Profiling and Event Trace Mapping
      7. 13.3.7  Debug and Device Management
        1. 13.3.7.1 Power-AP Overview
        2. 13.3.7.2 Subdomain Level Status and Control
          1. 13.3.7.2.1 Subdomain Power Status and Control
            1. 13.3.7.2.1.1 Subdomain Power Status
            2. 13.3.7.2.1.2 Subdomain Power Control
          2. 13.3.7.2.2 Subdomain Clock Status and Control
            1. 13.3.7.2.2.1 Subdomain Clock Status
            2. 13.3.7.2.2.2 Subdomain Clock Control
          3. 13.3.7.2.3 Subdomain Reset Status and Control
            1. 13.3.7.2.3.1 Subdomain Reset Status
            2. 13.3.7.2.3.2 Subdomain Reset Control
            3. 13.3.7.2.3.3 Subdomain Wait-in-Reset
          4. 13.3.7.2.4 Subdomain Execution Control and Status
            1. 13.3.7.2.4.1 Subdomain Debug Connection
            2. 13.3.7.2.4.2 Subdomain Debug Status
            3. 13.3.7.2.4.3 Subdomain Debug Execution Control
        3. 13.3.7.3 System Level Status and Control
          1. 13.3.7.3.1 System Level Generic Data
          2. 13.3.7.3.2 System Level Reset Control and Status
          3. 13.3.7.3.3 System Level Connect Control
            1. 13.3.7.3.3.1 System Level Reset Status
            2. 13.3.7.3.3.2 System Level Reset Control
            3. 13.3.7.3.3.3 System Level Wait-in-Reset
          4. 13.3.7.3.4 System Level Execution Control
      8. 13.3.8  Debug Cross Trigger Network
        1. 13.3.8.1 Debug Cell CTI Trigger Mapping
      9. 13.3.9  Debug Suspend
      10. 13.3.10 Debug Time Distribution
      11. 13.3.11 Debug Wakeup
      12. 13.3.12 Debug and Safety
    4. 13.4 Compute Cluster Debug
      1. 13.4.1 Debug at the Compute Cluster Level
      2. 13.4.2 Debug at the A72SS Level
        1. 13.4.2.1 A72SS Debug Features
        2. 13.4.2.2 A72SS Debug Modes
        3. 13.4.2.3 A72SS Processor Trace
        4. 13.4.2.4 A72SS Performance Monitoring
        5. 13.4.2.5 A72SS Cross Triggering
      3. 13.4.3 Debug at the C71SS Level
      4. 13.4.4 Debug at the MSMC Level
        1. 13.4.4.1 MSMC Probes
        2. 13.4.4.2 MSMC CTSET Events
        3. 13.4.4.3 MSMC Cross Triggering
    5. 13.5 R5FSS Debug
      1. 13.5.1 R5FSS Debug Features
      2. 13.5.2 R5FSS Processor Trace
      3. 13.5.3 R5FSS Performance Monitoring
      4. 13.5.4 R5FSS Cross Triggering
    6. 13.6 Debug Memory Map
    7. 13.7 Application Support
  16. 14Revision History

2.1 Memory Map

Table 2-1 MAIN Memory Map
Region NameStart AddressEnd AddressSize
PSRAM2KECC0_RAM 0x0000000000 0x0000000800 2 KB
CTRL_MMR0_CFG0 0x0000100000 0x0000120000 128 KB
PSRAMECC0_RAM 0x0000200000 0x0000200400 1 KB
PSC0 0x0000400000 0x0000401000 4 KB
PLLCTRL0 0x0000410000 0x0000410200 512 B
AM_BOLT_PSC_WRAP0_VBUS 0x0000420000 0x0000421000 4 KB
GPIO0 0x0000600000 0x0000600100 256 B
GPIO2 0x0000610000 0x0000610100 256 B
GPIO4 0x0000620000 0x0000620100 256 B
GPIO6 0x0000630000 0x0000630100 256 B
PLL0_CFG 0x0000680000 0x00006A0000 128 KB
ESM0_CFG 0x0000700000 0x0000701000 4 KB
AM_MAIN_INFRA_TO_MAIN_INFRA_STOG0_CFG 0x0000780000 0x0000780400 1 KB
DCC0 0x0000800000 0x0000800040 64 B
DCC1 0x0000804000 0x0000804040 64 B
DCC2 0x0000808000 0x0000808040 64 B
DCC3 0x000080C000 0x000080C040 64 B
DCC4 0x0000810000 0x0000810040 64 B
DCC5 0x0000814000 0x0000814040 64 B
DCC6 0x0000818000 0x0000818040 64 B
DCC7 0x000081C000 0x000081C040 64 B
DCC8 0x0000820000 0x0000820040 64 B
DCC9 0x0000824000 0x0000824040 64 B
GPIOMUX_INTRTR0_CFG 0x0000A00000 0x0000A00800 2 KB
CMPEVENT_INTRTR0_CFG 0x0000A30000 0x0000A30200 512 B
TIMESYNC_INTRTR0_INTR_ROUTER_CFG 0x0000A40000 0x0000A40800 2 KB
GTC0_GTC_CFG0 0x0000A80000 0x0000A80400 1 KB
GTC0_GTC_CFG1 0x0000A90000 0x0000A94000 16 KB
GTC0_GTC_CFG2 0x0000AA0000 0x0000AA4000 16 KB
GTC0_GTC_CFG3 0x0000AB0000 0x0000AB4000 16 KB
MAIN_CBASS0_ERR 0x0000B00000 0x0000B00400 1 KB
CBASS_INFRA_NON_SAFE0_ERR 0x0000B04000 0x0000B04400 1 KB
CBASS_FW0_ERR 0x0000B08000 0x0000B08400 1 KB
PSRAMECC0_ECC_AGGR 0x0000C00000 0x0000C00400 1 KB
PSRAM2KECC0_ECC_AGGR 0x0000C01000 0x0000C01400 1 KB
ECC_AGGR0_ECC_AGGR 0x0000C02000 0x0000C02400 1 KB
PBIST0 0x0000D00000 0x0000D00400 1 KB
DFTSS0 0x0000D10000 0x0000D10400 1 KB
PBIST1 0x0000D20000 0x0000D20400 1 KB
PBIST4 0x0000D30000 0x0000D30400 1 KB
COMPUTE_CLUSTERHP0_GIC_TRANSLATER 0x0001000000 0x0001400000 4 MB
COMPUTE_CLUSTERHP0_GIC_DISTRIBUTOR 0x0001800000 0x0001810000 64 KB
COMPUTE_CLUSTERHP0_GIC_MESSAGE_BASED_SPIS 0x0001810000 0x0001820000 64 KB
COMPUTE_CLUSTERHP0_GIC_ITS 0x0001820000 0x0001830000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_0 0x0001900000 0x0001910000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_0 0x0001910000 0x0001920000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_1 0x0001920000 0x0001930000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_1 0x0001930000 0x0001940000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_2 0x0001940000 0x0001950000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_2 0x0001950000 0x0001960000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_3 0x0001960000 0x0001970000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_3 0x0001970000 0x0001980000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_4 0x0001980000 0x0001990000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_4 0x0001990000 0x00019A0000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_5 0x00019A0000 0x00019B0000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_5 0x00019B0000 0x00019C0000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_6 0x00019C0000 0x00019D0000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_6 0x00019D0000 0x00019E0000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_CONTROL_LPI_7 0x00019E0000 0x00019F0000 64 KB
COMPUTE_CLUSTERHP0_GIC_REDISTRIBUTOR_SGI_PPI_7 0x00019F0000 0x0001A00000 64 KB
I2C0_CFG 0x0002000000 0x0002000100 256 B
I2C1_CFG 0x0002010000 0x0002010100 256 B
I2C2_CFG 0x0002020000 0x0002020100 256 B
I2C3_CFG 0x0002030000 0x0002030100 256 B
I2C4_CFG 0x0002040000 0x0002040100 256 B
I2C5_CFG 0x0002050000 0x0002050100 256 B
I2C6_CFG 0x0002060000 0x0002060100 256 B
MCSPI0_CFG 0x0002100000 0x0002100400 1 KB
MCSPI1_CFG 0x0002110000 0x0002110400 1 KB
MCSPI2_CFG 0x0002120000 0x0002120400 1 KB
MCSPI3_CFG 0x0002130000 0x0002130400 1 KB
MCSPI4_CFG 0x0002140000 0x0002140400 1 KB
MCSPI5_CFG 0x0002150000 0x0002150400 1 KB
MCSPI6_CFG 0x0002160000 0x0002160400 1 KB
MCSPI7_CFG 0x0002170000 0x0002170400 1 KB
RTI0_CFG 0x0002200000 0x0002200100 256 B
RTI1_CFG 0x0002210000 0x0002210100 256 B
RTI2_CFG 0x0002220000 0x0002220100 256 B
RTI3_CFG 0x0002230000 0x0002230100 256 B
RTI4_CFG 0x0002240000 0x0002240100 256 B
RTI5_CFG 0x0002250000 0x0002250100 256 B
RTI6_CFG 0x0002260000 0x0002260100 256 B
RTI7_CFG 0x0002270000 0x0002270100 256 B
RTI15_CFG 0x00022F0000 0x00022F0100 256 B
RTI16_CFG 0x0002300000 0x0002300100 256 B
RTI17_CFG 0x0002310000 0x0002310100 256 B
RTI18_CFG 0x0002320000 0x0002320100 256 B
RTI19_CFG 0x0002330000 0x0002330100 256 B
RTI28_CFG 0x00023C0000 0x00023C0100 256 B
RTI29_CFG 0x00023D0000 0x00023D0100 256 B
RTI30_CFG 0x00023E0000 0x00023E0100 256 B
RTI31_CFG 0x00023F0000 0x00023F0100 256 B
TIMER0_CFG 0x0002400000 0x0002400400 1 KB
TIMER1_CFG 0x0002410000 0x0002410400 1 KB
TIMER2_CFG 0x0002420000 0x0002420400 1 KB
TIMER3_CFG 0x0002430000 0x0002430400 1 KB
TIMER4_CFG 0x0002440000 0x0002440400 1 KB
TIMER5_CFG 0x0002450000 0x0002450400 1 KB
TIMER6_CFG 0x0002460000 0x0002460400 1 KB
TIMER7_CFG 0x0002470000 0x0002470400 1 KB
TIMER8_CFG 0x0002480000 0x0002480400 1 KB
TIMER9_CFG 0x0002490000 0x0002490400 1 KB
TIMER10_CFG 0x00024A0000 0x00024A0400 1 KB
TIMER11_CFG 0x00024B0000 0x00024B0400 1 KB
TIMER12_CFG 0x00024C0000 0x00024C0400 1 KB
TIMER13_CFG 0x00024D0000 0x00024D0400 1 KB
TIMER14_CFG 0x00024E0000 0x00024E0400 1 KB
TIMER15_CFG 0x00024F0000 0x00024F0400 1 KB
TIMER16_CFG 0x0002500000 0x0002500400 1 KB
TIMER17_CFG 0x0002510000 0x0002510400 1 KB
TIMER18_CFG 0x0002520000 0x0002520400 1 KB
TIMER19_CFG 0x0002530000 0x0002530400 1 KB
RTI32_CFG 0x0002540000 0x0002540100 256 B
RTI33_CFG 0x0002550000 0x0002550100 256 B
AM_HC2_TO_HC_CFG_STOG5_CFG 0x0002604000 0x0002604400 1 KB
AM_RC_TO_HC2_STOG7_CFG 0x0002606000 0x0002606400 1 KB
AM_RC_TO_RC_CFG_STOG3_CFG 0x0002608000 0x0002608400 1 KB
AM_IPPHY_TO_IPPHY_STOG1_CFG 0x000260A000 0x000260A400 1 KB
AM_RC_TO_HC2_STOG6_CFG 0x000260C000 0x000260C400 1 KB
AM_NAVSS_TO_AC_NON_SAFE_STOG4_CFG 0x0002610000 0x0002610400 1 KB
AM_AC_CFG_TO_AC_CFG_NON_SAFE_STOG2_CFG 0x0002612000 0x0002612400 1 KB
AM_AC_CFG_TO_AC_CFG_NON_SAFE_STOG9_CFG 0x0002614000 0x0002614400 1 KB
AM_IPPHY_TO_RTI_GPU_STOG8_CFG 0x0002616000 0x0002616400 1 KB
MCAN14_SS 0x0002680000 0x0002680100 256 B
MCAN14_CFG 0x0002681000 0x0002681200 512 B
MCAN14_MSGMEM_RAM 0x0002688000 0x0002690000 32 KB
MCAN15_SS 0x0002690000 0x0002690100 256 B
MCAN15_CFG 0x0002691000 0x0002691200 512 B
MCAN15_MSGMEM_RAM 0x0002698000 0x00026A0000 32 KB
MCAN16_SS 0x00026A0000 0x00026A0100 256 B
MCAN16_CFG 0x00026A1000 0x00026A1200 512 B
MCAN16_MSGMEM_RAM 0x00026A8000 0x00026B0000 32 KB
MCAN17_SS 0x00026B0000 0x00026B0100 256 B
MCAN17_CFG 0x00026B1000 0x00026B1200 512 B
MCAN17_MSGMEM_RAM 0x00026B8000 0x00026C0000 32 KB
MCAN0_SS 0x0002700000 0x0002700100 256 B
MCAN0_CFG 0x0002701000 0x0002701200 512 B
MCAN0_MSGMEM_RAM 0x0002708000 0x0002710000 32 KB
MCAN1_SS 0x0002710000 0x0002710100 256 B
MCAN1_CFG 0x0002711000 0x0002711200 512 B
MCAN1_MSGMEM_RAM 0x0002718000 0x0002720000 32 KB
MCAN2_SS 0x0002720000 0x0002720100 256 B
MCAN2_CFG 0x0002721000 0x0002721200 512 B
MCAN2_MSGMEM_RAM 0x0002728000 0x0002730000 32 KB
MCAN3_SS 0x0002730000 0x0002730100 256 B
MCAN3_CFG 0x0002731000 0x0002731200 512 B
MCAN3_MSGMEM_RAM 0x0002738000 0x0002740000 32 KB
MCAN4_SS 0x0002740000 0x0002740100 256 B
MCAN4_CFG 0x0002741000 0x0002741200 512 B
MCAN4_MSGMEM_RAM 0x0002748000 0x0002750000 32 KB
MCAN5_SS 0x0002750000 0x0002750100 256 B
MCAN5_CFG 0x0002751000 0x0002751200 512 B
MCAN5_MSGMEM_RAM 0x0002758000 0x0002760000 32 KB
MCAN6_SS 0x0002760000 0x0002760100 256 B
MCAN6_CFG 0x0002761000 0x0002761200 512 B
MCAN6_MSGMEM_RAM 0x0002768000 0x0002770000 32 KB
MCAN7_SS 0x0002770000 0x0002770100 256 B
MCAN7_CFG 0x0002771000 0x0002771200 512 B
MCAN7_MSGMEM_RAM 0x0002778000 0x0002780000 32 KB
MCAN8_SS 0x0002780000 0x0002780100 256 B
MCAN8_CFG 0x0002781000 0x0002781200 512 B
MCAN8_MSGMEM_RAM 0x0002788000 0x0002790000 32 KB
MCAN9_SS 0x0002790000 0x0002790100 256 B
MCAN9_CFG 0x0002791000 0x0002791200 512 B
MCAN9_MSGMEM_RAM 0x0002798000 0x00027A0000 32 KB
MCAN10_SS 0x00027A0000 0x00027A0100 256 B
MCAN10_CFG 0x00027A1000 0x00027A1200 512 B
MCAN10_MSGMEM_RAM 0x00027A8000 0x00027B0000 32 KB
MCAN11_SS 0x00027B0000 0x00027B0100 256 B
MCAN11_CFG 0x00027B1000 0x00027B1200 512 B
MCAN11_MSGMEM_RAM 0x00027B8000 0x00027C0000 32 KB
MCAN12_SS 0x00027C0000 0x00027C0100 256 B
MCAN12_CFG 0x00027C1000 0x00027C1200 512 B
MCAN12_MSGMEM_RAM 0x00027C8000 0x00027D0000 32 KB
MCAN13_SS 0x00027D0000 0x00027D0100 256 B
MCAN13_CFG 0x00027D1000 0x00027D1200 512 B
MCAN13_MSGMEM_RAM 0x00027D8000 0x00027E0000 32 KB
PDMA5_REGS 0x00027E0000 0x00027E0400 1 KB
PDMA6_REGS 0x00027E1000 0x00027E1400 1 KB
PDMA7_REGS 0x00027E2000 0x00027E2400 1 KB
UART0 0x0002800000 0x0002800200 512 B
UART1 0x0002810000 0x0002810200 512 B
UART2 0x0002820000 0x0002820200 512 B
UART3 0x0002830000 0x0002830200 512 B
UART4 0x0002840000 0x0002840200 512 B
UART5 0x0002850000 0x0002850200 512 B
UART6 0x0002860000 0x0002860200 512 B
UART7 0x0002870000 0x0002870200 512 B
UART8 0x0002880000 0x0002880200 512 B
UART9 0x0002890000 0x0002890200 512 B
PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG 0x0002900000 0x0002901000 4 KB
PCIE0_CORE_VMAP_MMRS 0x0002904000 0x0002905000 4 KB
PCIE0_CORE_CPTS_CFG_CPTS_VBUSP 0x0002906000 0x0002906400 1 KB
PCIE0_CORE_USER_CFG_USER_CFG 0x0002907000 0x0002907400 1 KB
PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG 0x0002910000 0x0002911000 4 KB
PCIE1_CORE_VMAP_MMRS 0x0002914000 0x0002915000 4 KB
PCIE1_CORE_ECC_AGGR0 0x0002915000 0x0002915400 1 KB
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP 0x0002916000 0x0002916400 1 KB
PCIE1_CORE_USER_CFG_USER_CFG 0x0002917000 0x0002917400 1 KB
PCIE2_CORE_PCIE_INTD_CFG_INTD_CFG 0x0002920000 0x0002921000 4 KB
PCIE2_CORE_VMAP_MMRS 0x0002924000 0x0002925000 4 KB
PCIE2_CORE_CPTS_CFG_CPTS_VBUSP 0x0002926000 0x0002926400 1 KB
PCIE2_CORE_USER_CFG_USER_CFG 0x0002927000 0x0002927400 1 KB
PCIE3_CORE_PCIE_INTD_CFG_INTD_CFG 0x0002930000 0x0002931000 4 KB
PCIE3_CORE_VMAP_MMRS 0x0002934000 0x0002935000 4 KB
PCIE3_CORE_CPTS_CFG_CPTS_VBUSP 0x0002936000 0x0002936400 1 KB
PCIE3_CORE_USER_CFG_USER_CFG 0x0002937000 0x0002937400 1 KB
VUSR_DUAL0_VUSR 0x0002960000 0x0002962000 8 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS0_SSCFG 0x0002980000 0x0002980200 512 B
COMPUTE_CLUSTERHP0_VBUSP_DDRSS0_CTLCFG 0x0002990000 0x0002998000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS1_SSCFG 0x00029A0000 0x00029A0200 512 B
COMPUTE_CLUSTERHP0_VBUSP_DDRSS1_CTLCFG 0x00029B0000 0x00029B8000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS2_SSCFG 0x00029C0000 0x00029C0200 512 B
COMPUTE_CLUSTERHP0_VBUSP_DDRSS2_CTLCFG 0x00029D0000 0x00029D8000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS3_SSCFG 0x00029E0000 0x00029E0200 512 B
COMPUTE_CLUSTERHP0_VBUSP_DDRSS3_CTLCFG 0x00029F0000 0x00029F8000 32 KB
PCIE0_CORE_ECC_AGGR0 0x0002A00000 0x0002A00400 1 KB
PCIE0_CORE_ECC_AGGR1 0x0002A01000 0x0002A01400 1 KB
PCIE1_CORE_ECC_AGGR1 0x0002A02000 0x0002A02400 1 KB
PCIE2_CORE_ECC_AGGR0 0x0002A04000 0x0002A04400 1 KB
PCIE2_CORE_ECC_AGGR1 0x0002A05000 0x0002A05400 1 KB
PCIE3_CORE_ECC_AGGR0 0x0002A06000 0x0002A06400 1 KB
PCIE3_CORE_ECC_AGGR1 0x0002A07000 0x0002A07400 1 KB
USB0_RAMS_INJ_CFG 0x0002A10000 0x0002A10400 1 KB
USB0_ECC_AGGR 0x0002A13000 0x0002A13400 1 KB
CPSW_9XUSSM0_CPSW_NUSS_VBUSP_ECC 0x0002A21000 0x0002A21400 1 KB
CPSW1_ECC 0x0002A22000 0x0002A22400 1 KB
SA2_UL0_ECC_AGGR 0x0002A23000 0x0002A23400 1 KB
MMCSD0_ECC_AGGR_RXMEM 0x0002A24000 0x0002A24400 1 KB
MMCSD0_ECC_AGGR_TXMEM 0x0002A25000 0x0002A25400 1 KB
MMCSD1_ECC_AGGR_RXMEM 0x0002A26000 0x0002A26400 1 KB
MMCSD1_ECC_AGGR_TXMEM 0x0002A27000 0x0002A27400 1 KB
UFS0_HCLK_ECC_AGGR_CFG 0x0002A28000 0x0002A28400 1 KB
UFS0_IPS_TCLK_ERR_INJ_CFG 0x0002A2A000 0x0002A2A400 1 KB
R5FSS0_EVNT_BUS_VBUSP_MMRS 0x0002A2D000 0x0002A2D100 256 B
R5FSS1_EVNT_BUS_VBUSP_MMRS 0x0002A2E000 0x0002A2E100 256 B
MSRAM_512K0_ECC_AGGR_REGS 0x0002A2F000 0x0002A2F400 1 KB
CSI_RX_IF0_ECC_AGGR_CFG 0x0002A30000 0x0002A30400 1 KB
CSI_RX_IF1_ECC_AGGR_CFG 0x0002A31000 0x0002A31400 1 KB
CSI_RX_IF2_ECC_AGGR_CFG 0x0002A32000 0x0002A32400 1 KB
R5FSS2_EVNT_BUS_VBUSP_MMRS 0x0002A33000 0x0002A33100 256 B
CSI_TX_IF_V2_0_ECC_AGGR_CFG 0x0002A38000 0x0002A38400 1 KB
CSI_TX_IF_V2_0_ECC_AGGR_BYTE_CFG 0x0002A38400 0x0002A38800 1 KB
CSI_TX_IF_V2_1_ECC_AGGR_CFG 0x0002A39000 0x0002A39400 1 KB
CSI_TX_IF_V2_1_ECC_AGGR_BYTE_CFG 0x0002A39400 0x0002A39800 1 KB
MCAN8_ECC_AGGR 0x0002A40000 0x0002A40400 1 KB
MCAN9_ECC_AGGR 0x0002A41000 0x0002A41400 1 KB
MCAN10_ECC_AGGR 0x0002A42000 0x0002A42400 1 KB
MCAN11_ECC_AGGR 0x0002A43000 0x0002A43400 1 KB
MCAN12_ECC_AGGR 0x0002A44000 0x0002A44400 1 KB
MCAN13_ECC_AGGR 0x0002A45000 0x0002A45400 1 KB
MCAN14_ECC_AGGR 0x0002A46000 0x0002A46400 1 KB
MCAN15_ECC_AGGR 0x0002A47000 0x0002A47400 1 KB
MCAN16_ECC_AGGR 0x0002A48000 0x0002A48400 1 KB
MCAN17_ECC_AGGR 0x0002A49000 0x0002A49400 1 KB
VPAC0_ECC_AGGR 0x0002A60000 0x0002A60400 1 KB
VPAC0_VISS_ECC_AGGR 0x0002A61000 0x0002A61400 1 KB
VPAC0_LDC_ECC_AGGR 0x0002A63000 0x0002A63400 1 KB
VPAC1_ECC_AGGR 0x0002A64000 0x0002A64400 1 KB
VPAC1_VISS_ECC_AGGR 0x0002A65000 0x0002A65400 1 KB
VPAC1_LDC_ECC_AGGR 0x0002A67000 0x0002A67400 1 KB
R5FSS0_CORE0_ECC_AGGR 0x0002A68000 0x0002A68400 1 KB
R5FSS1_CORE0_ECC_AGGR 0x0002A69000 0x0002A69400 1 KB
DMPAC0_ECC_AGGR 0x0002A6A000 0x0002A6A400 1 KB
R5FSS2_CORE0_ECC_AGGR 0x0002A6B000 0x0002A6B400 1 KB
MCAN0_ECC_AGGR 0x0002A78000 0x0002A78400 1 KB
MCAN1_ECC_AGGR 0x0002A79000 0x0002A79400 1 KB
MCAN2_ECC_AGGR 0x0002A7A000 0x0002A7A400 1 KB
MCAN3_ECC_AGGR 0x0002A7B000 0x0002A7B400 1 KB
MCAN4_ECC_AGGR 0x0002A7C000 0x0002A7C400 1 KB
MCAN5_ECC_AGGR 0x0002A7D000 0x0002A7D400 1 KB
MCAN6_ECC_AGGR 0x0002A7E000 0x0002A7E400 1 KB
MCAN7_ECC_AGGR 0x0002A7F000 0x0002A7F400 1 KB
CBASS_DEBUG0_ERR 0x0002A80000 0x0002A80400 1 KB
CBASS_HC2_0_ERR 0x0002A83000 0x0002A83400 1 KB
CBASS_AC_CFG0_ERR 0x0002A84000 0x0002A84400 1 KB
CBASS_AC_NONSAFE0_ERR 0x0002A85000 0x0002A85400 1 KB
CBASS_DATADEBUG0_ERR 0x0002A86000 0x0002A86400 1 KB
CBASS_CSI0_ERR 0x0002A88000 0x0002A88400 1 KB
CBASS_HC_CFG0_ERR 0x0002A89000 0x0002A89400 1 KB
CBASS_RC0_ERR 0x0002A8C000 0x0002A8C400 1 KB
CBASS_RC_CFG0_ERR 0x0002A8D000 0x0002A8D400 1 KB
CBASS_IPPHY0_ERR 0x0002A8F000 0x0002A8F400 1 KB
AM_PULSAR0_MEM_CBASS0_ERR 0x0002A90000 0x0002A90400 1 KB
AM_PULSAR0_SLV_CBASS0_ERR 0x0002A91000 0x0002A91400 1 KB
AM_PULSAR1_MEM_CBASS0_ERR 0x0002A92000 0x0002A92400 1 KB
CBASS_IPPHY_SAFE0_ERR 0x0002A94000 0x0002A94400 1 KB
AM_PULSAR1_PERIPH_SWITCH_CBASS0_ERR 0x0002A95000 0x0002A95400 1 KB
CBASS_AC_CFG_NONSAFE0_ERR 0x0002A97000 0x0002A97400 1 KB
AM_AC_MERGER_CBASS0_ERR 0x0002A98000 0x0002A98400 1 KB
DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG 0x0002AC0000 0x0002AC0400 1 KB
DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG 0x0002AC1000 0x0002AC1400 1 KB
DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG 0x0002AC2000 0x0002AC2400 1 KB
IVC_DOM0_ECC_AGGR20_REGS 0x0002AE0000 0x0002AE0400 1 KB
IVC_DOM1_ECC_AGGR21_REGS 0x0002AE1000 0x0002AE1400 1 KB
IVC_DOM0_ECC_AGGR16_REGS 0x0002AF0000 0x0002AF0400 1 KB
IVC_DOM1_ECC_AGGR17_REGS 0x0002AF1000 0x0002AF1400 1 KB
IVC_DOM0_ECC_AGGR18_REGS 0x0002AF2000 0x0002AF2400 1 KB
IVC_DOM1_ECC_AGGR19_REGS 0x0002AF3000 0x0002AF3400 1 KB
ECC_AGGR4_ECC_AGGR 0x0002AF4000 0x0002AF4400 1 KB
ECC_AGGR5_ECC_AGGR 0x0002AF5000 0x0002AF5400 1 KB
MAIN_IP_ECC_AGGR0_ECC_AGGR 0x0002AF6000 0x0002AF6400 1 KB
ECC_AGGR6_ECC_AGGR 0x0002AF7000 0x0002AF7400 1 KB
ECC_AGGR9_ECC_AGGR 0x0002AF9000 0x0002AF9400 1 KB
ECC_AGGR10_ECC_AGGR 0x0002AFA000 0x0002AFA400 1 KB
ECC_AGGR11_ECC_AGGR 0x0002AFB000 0x0002AFB400 1 KB
MSRAM_512K1_ECC_AGGR_REGS 0x0002AFC000 0x0002AFC400 1 KB
VUSR_DUAL0_REGS 0x0002AFD000 0x0002AFD400 1 KB
MSRAM_512K2_ECC_AGGR_REGS 0x0002AFF000 0x0002AFF400 1 KB
MCASP0_CFG 0x0002B00000 0x0002B02000 8 KB
MCASP0_DMA 0x0002B08000 0x0002B08400 1 KB
MCASP1_CFG 0x0002B10000 0x0002B12000 8 KB
MCASP1_DMA 0x0002B18000 0x0002B18400 1 KB
MCASP2_CFG 0x0002B20000 0x0002B22000 8 KB
MCASP2_DMA 0x0002B28000 0x0002B28400 1 KB
MCASP3_CFG 0x0002B30000 0x0002B32000 8 KB
MCASP3_DMA 0x0002B38000 0x0002B38400 1 KB
MCASP4_CFG 0x0002B40000 0x0002B42000 8 KB
MCASP4_DMA 0x0002B48000 0x0002B48400 1 KB
EPWM0_EPWM 0x0003000000 0x0003000100 256 B
EPWM1_EPWM 0x0003010000 0x0003010100 256 B
EPWM2_EPWM 0x0003020000 0x0003020100 256 B
EPWM3_EPWM 0x0003030000 0x0003030100 256 B
EPWM4_EPWM 0x0003040000 0x0003040100 256 B
EPWM5_EPWM 0x0003050000 0x0003050100 256 B
ECAP0_CTL_STS 0x0003100000 0x0003100100 256 B
ECAP1_CTL_STS 0x0003110000 0x0003110100 256 B
ECAP2_CTL_STS 0x0003120000 0x0003120100 256 B
ATL0_REG 0x00031F0000 0x00031F0400 1 KB
EQEP0_REG 0x0003200000 0x0003200100 256 B
EQEP1_REG 0x0003210000 0x0003210100 256 B
EQEP2_REG 0x0003220000 0x0003220100 256 B
PBIST7 0x0003300000 0x0003300400 1 KB
PBIST8 0x0003310000 0x0003310400 1 KB
PBIST5 0x0003340000 0x0003340400 1 KB
PBIST11 0x0003350000 0x0003350400 1 KB
PBIST13 0x0003360000 0x0003360400 1 KB
PBIST3 0x0003370000 0x0003370400 1 KB
PBIST2 0x0003380000 0x0003380400 1 KB
PBIST10 0x0003390000 0x0003390400 1 KB
AEP_GPU_BXS464_WRAP0_MEM 0x00033A0000 0x00033A0400 1 KB
PBIST14 0x00033C0000 0x00033C0400 1 KB
PBIST15 0x00033D0000 0x00033D0400 1 KB
MAIN_USART_PSILSS0_MMRS 0x0003400000 0x0003401000 4 KB
CPSW_PSILSS0_MMRS 0x0003404000 0x0003405000 4 KB
DEBUG_PSILSS0_MMRS 0x0003408000 0x0003409000 4 KB
CSI_PSILSS0_MMRS 0x0003410000 0x0003411000 4 KB
SA2_CPSW_PSILSS0_MMRS 0x0003414000 0x0003415000 4 KB
DMPAC_VPAC_PSILSS0_MMRS 0x000341C000 0x000341D000 4 KB
NAVSS0_NBSS_CFG_REGS0_MMRS 0x0003700000 0x0003700100 256 B
NAVSS0_NBSS_CFG_ECCAGGR0_REGS 0x0003701000 0x0003701400 1 KB
NAVSS0_NBSS_NB0_CFG_MMRS 0x0003702000 0x0003702100 256 B
NAVSS0_NBSS_NB1_CFG_MMRS 0x0003703000 0x0003703100 256 B
NAVSS0_NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS 0x0003710000 0x0003710100 256 B
VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS 0x0003800000 0x0003800400 1 KB
VPAC0_CTSET2_WRAP_CFG_CTSET2_CFG 0x0003802000 0x0003804000 8 KB
VPAC0_CP_INTD_CFG_INTD_CFG 0x0003804000 0x0003805000 4 KB
VPAC0_HTS_S_VBUSP 0x0003810000 0x0003820000 64 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP 0x0003820000 0x0003820400 1 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP 0x0003820400 0x0003820600 512 B
VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT 0x0003820800 0x0003821000 2 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT 0x0003821000 0x0003821800 2 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM 0x0003822000 0x0003824000 8 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM 0x0003828000 0x0003830000 32 KB
VPAC0_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM 0x0003830000 0x0003838000 32 KB
VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP 0x00038C0000 0x00038C0800 2 KB
VPAC0_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP 0x00038C0800 0x00038C0A00 512 B
VPAC0_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG 0x00038C2000 0x00038C3000 4 KB
VPAC0_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP 0x00038C3000 0x00038C3200 512 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP 0x0003900000 0x0003900200 512 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP 0x0003900400 0x0003900600 512 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE 0x0003903800 0x0003904000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM 0x0003904000 0x0003908000 16 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA 0x0003908000 0x0003910000 32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC 0x0003910000 0x0003910800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1 0x0003910800 0x0003911000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2 0x0003911000 0x0003911800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3 0x0003911800 0x0003912000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8 0x0003912000 0x0003912800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8 0x0003912800 0x0003913000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8 0x0003913000 0x0003913800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST 0x0003913800 0x0003914000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE 0x0003918000 0x0003918800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG 0x0003920000 0x0003920400 1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG 0x0003920400 0x0003920500 256 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT3_RAM_RAWFE_PWL_LUT3_RAM 0x0003920800 0x0003921000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT2_RAM_RAWFE_PWL_LUT2_RAM 0x0003921000 0x0003921800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT1_RAM_RAWFE_PWL_LUT1_RAM 0x0003921800 0x0003922000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_WDR_LUT_RAM_RAWFE_WDR_LUT_RAM 0x0003922000 0x0003922800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_LUT_RAM_RAWFE_H3A_LUT_RAM 0x0003922800 0x0003923000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_RAM_RAWFE_DPC_LUT_RAM 0x0003923000 0x0003923400 1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_LRAM_RAWFE_DPC_LRAM 0x0003924000 0x0003926000 8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LSC_RAM_RAWFE_LSC_LUT_RAM 0x0003928000 0x0003930000 32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_ARAM_RAWFE_H3A_ARAM 0x0003930000 0x0003932000 8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_LRAM_RAWFE_H3A_LRAM 0x0003932000 0x0003934000 8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE 0x0003940000 0x0003940800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTDATA_VBUSP_RAWHIST 0x0003940800 0x0003940A00 512 B
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTLUT_VBUSP_RAWHIST_LUT 0x0003941000 0x0003941800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM 0x0003944000 0x0003948000 16 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE 0x0003950000 0x0003958000 32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA_DLUTS 0x0003958000 0x000395C000 16 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_DLUTS 0x000395C000 0x0003960000 16 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_EE_VBUSP_FLEXEE 0x0003960000 0x0003968000 32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA 0x0003968000 0x0003970000 32 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC 0x0003970000 0x0003970800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC1 0x0003970800 0x0003971000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC2 0x0003971000 0x0003971800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC3 0x0003971800 0x0003972000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_Y8R8 0x0003972000 0x0003972800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_C8G8 0x0003972800 0x0003973000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_S8B8 0x0003973000 0x0003973800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_HIST 0x0003973800 0x0003974000 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_LINE 0x0003978000 0x0003978800 2 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC 0x0003980000 0x0003980400 1 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_CORE_LUT_CFG_LUT_MEM 0x0003982000 0x0003984000 8 KB
VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_LINEMEM_CFG_LINE_MEM 0x0003984000 0x0003988000 16 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU 0x0003A00000 0x0003A04000 16 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET 0x0003A04000 0x0003A08000 16 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE 0x0003A08000 0x0003A10000 32 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT 0x0003A40000 0x0003A60000 128 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT 0x0003A60000 0x0003A80000 128 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG 0x0003A80000 0x0003AA0000 128 KB
VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE 0x0003AE0000 0x0003B00000 128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU 0x0003B00000 0x0003B04000 16 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET 0x0003B04000 0x0003B08000 16 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE 0x0003B08000 0x0003B10000 32 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT 0x0003B40000 0x0003B60000 128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT 0x0003B60000 0x0003B80000 128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG 0x0003B80000 0x0003BA0000 128 KB
VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE 0x0003BE0000 0x0003C00000 128 KB
VPAC1_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS 0x0003C00000 0x0003C00400 1 KB
VPAC1_CTSET2_WRAP_CFG_CTSET2_CFG 0x0003C02000 0x0003C04000 8 KB
VPAC1_CP_INTD_CFG_INTD_CFG 0x0003C04000 0x0003C05000 4 KB
VPAC1_HTS_S_VBUSP 0x0003C10000 0x0003C20000 64 KB
VPAC1_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP 0x0003C20000 0x0003C20400 1 KB
VPAC1_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP 0x0003C20400 0x0003C20600 512 B
VPAC1_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALY_LUTCFG_DUALY_LUT 0x0003C20800 0x0003C21000 2 KB
VPAC1_PAR_VPAC_LDC0_S_VBUSP_PIXWRINTF_DUALC_LUTCFG_DUALC_LUT 0x0003C21000 0x0003C21800 2 KB
VPAC1_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_MESH_VBUSPI_MESH_MEM 0x0003C22000 0x0003C24000 8 KB
VPAC1_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_Y_VBUSPI_Y_MEM 0x0003C28000 0x0003C30000 32 KB
VPAC1_PAR_VPAC_LDC0_S_VBUSP_MEMCFG_LOOP_CBCR_VBUSPI_CBCR_MEM 0x0003C30000 0x0003C38000 32 KB
VPAC1_PAR_VPAC_MSC_CFG_VP_CFG_VP 0x0003CC0000 0x0003CC0800 2 KB
VPAC1_PAR_VPAC_MSC_CFG_VP_LSE_CFG_VP 0x0003CC0800 0x0003CC0A00 512 B
VPAC1_PAR_VPAC_NF_S_VBUSP_MMR_VBUSP_NF_CFG 0x0003CC2000 0x0003CC3000 4 KB
VPAC1_PAR_VPAC_NF_S_VBUSP_VPAC_NF_LSE_CFG_VP 0x0003CC3000 0x0003CC3200 512 B
VPAC1_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP 0x0003D00000 0x0003D00200 512 B
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VPAC_VISS_LSE_CFG_VP 0x0003D00400 0x0003D00600 512 B
VPAC1_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_CFG_GLBCE 0x0003D03800 0x0003D04000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_K3_GLBCE_TOP_STATMEM_CFG_GLBCE_STATMEM 0x0003D04000 0x0003D08000 16 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA 0x0003D08000 0x0003D10000 32 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC 0x0003D10000 0x0003D10800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC1 0x0003D10800 0x0003D11000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC2 0x0003D11000 0x0003D11800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_CONTRASTC3 0x0003D11800 0x0003D12000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_Y8R8 0x0003D12000 0x0003D12800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_C8G8 0x0003D12800 0x0003D13000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_S8B8 0x0003D13000 0x0003D13800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_HIST 0x0003D13800 0x0003D14000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_FCC_VBUSP_FLEXCC_LINE 0x0003D18000 0x0003D18800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_MMR_S_VBUSP_RAWFE_CFG 0x0003D20000 0x0003D20400 1 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_CFG_RAWFE_H3A_CFG 0x0003D20400 0x0003D20500 256 B
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT3_RAM_RAWFE_PWL_LUT3_RAM 0x0003D20800 0x0003D21000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT2_RAM_RAWFE_PWL_LUT2_RAM 0x0003D21000 0x0003D21800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LUT1_RAM_RAWFE_PWL_LUT1_RAM 0x0003D21800 0x0003D22000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_WDR_LUT_RAM_RAWFE_WDR_LUT_RAM 0x0003D22000 0x0003D22800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_LUT_RAM_RAWFE_H3A_LUT_RAM 0x0003D22800 0x0003D23000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_RAM_RAWFE_DPC_LUT_RAM 0x0003D23000 0x0003D23400 1 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_DPC_LRAM_RAWFE_DPC_LRAM 0x0003D24000 0x0003D26000 8 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_LSC_RAM_RAWFE_LSC_LUT_RAM 0x0003D28000 0x0003D30000 32 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_ARAM_RAWFE_H3A_ARAM 0x0003D30000 0x0003D32000 8 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_RAWFE_CFG_H3A_WRAP_LRAM_RAWFE_H3A_LRAM 0x0003D32000 0x0003D34000 8 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MMR_VBUSP_NSF4VCORE 0x0003D40000 0x0003D40800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTDATA_VBUSP_RAWHIST 0x0003D40800 0x0003D40A00 512 B
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_RAWHIST_HISTLUT_VBUSP_RAWHIST_LUT 0x0003D41000 0x0003D41800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_NSF4V_CFG_MEM_MMRRAM_VBUSP_MMR_RAM 0x0003D44000 0x0003D48000 16 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_EE_VBUSP_FLEXEE 0x0003D50000 0x0003D58000 32 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP_CFA_VBUSP_FLEXCFA_DLUTS 0x0003D58000 0x0003D5C000 16 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_DLUTS 0x0003D5C000 0x0003D60000 16 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_EE_VBUSP_FLEXEE 0x0003D60000 0x0003D68000 32 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA 0x0003D68000 0x0003D70000 32 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC 0x0003D70000 0x0003D70800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC1 0x0003D70800 0x0003D71000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC2 0x0003D71000 0x0003D71800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_CONTRASTC3 0x0003D71800 0x0003D72000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_Y8R8 0x0003D72000 0x0003D72800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_C8G8 0x0003D72800 0x0003D73000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_S8B8 0x0003D73000 0x0003D73800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_HIST 0x0003D73800 0x0003D74000 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_FCC_VBUSP_FLEXCC_LINE 0x0003D78000 0x0003D78800 2 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC 0x0003D80000 0x0003D80400 1 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_CORE_LUT_CFG_LUT_MEM 0x0003D82000 0x0003D84000 8 KB
VPAC1_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_LINEMEM_CFG_LINE_MEM 0x0003D84000 0x0003D88000 16 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU 0x0003E00000 0x0003E04000 16 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_SET 0x0003E04000 0x0003E08000 16 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE 0x0003E08000 0x0003E10000 32 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT 0x0003E40000 0x0003E60000 128 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHRT 0x0003E60000 0x0003E80000 128 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG 0x0003E80000 0x0003EA0000 128 KB
VPAC1_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE 0x0003EE0000 0x0003F00000 128 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU 0x0003F00000 0x0003F04000 16 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_SET 0x0003F04000 0x0003F08000 16 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE 0x0003F08000 0x0003F10000 32 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT 0x0003F40000 0x0003F60000 128 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHRT 0x0003F60000 0x0003F80000 128 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG 0x0003F80000 0x0003FA0000 128 KB
VPAC1_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CAUSE 0x0003FE0000 0x0004000000 128 KB
USB0_MMR_MMRVBP_USBSS_CMN 0x0004104000 0x0004104100 256 B
USB0_PHY2 0x0004108000 0x0004108400 1 KB
CODEC0_VPU 0x0004210000 0x0004220000 64 KB
CODEC1_VPU 0x0004220000 0x0004230000 64 KB
CSI_TX_IF_V2_0_TX_SHIM_VBUSP_MMR_CSI2TXIF_V2 0x0004400000 0x0004401000 4 KB
CSI_TX_IF_V2_0_VBUS2APB_WRAP_VBUSP_APB_CSI2TX_V2 0x0004404000 0x0004405000 4 KB
CSI_TX_IF_V2_0_CP_INTD_CFG_INTD_CFG 0x0004408000 0x0004409000 4 KB
CSI_TX_IF_V2_1_TX_SHIM_VBUSP_MMR_CSI2TXIF_V2 0x0004410000 0x0004411000 4 KB
CSI_TX_IF_V2_1_VBUS2APB_WRAP_VBUSP_APB_CSI2TX_V2 0x0004414000 0x0004415000 4 KB
CSI_TX_IF_V2_1_CP_INTD_CFG_INTD_CFG 0x0004418000 0x0004419000 4 KB
DPHY_TX0 0x0004480000 0x0004481000 4 KB
DPHY_TX1 0x0004481000 0x0004482000 4 KB
CSI_RX_IF0_RX_SHIM_VBUSP_MMR_CSI2RXIF 0x0004500000 0x0004501000 4 KB
CSI_RX_IF0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX 0x0004504000 0x0004505000 4 KB
CSI_RX_IF0_CP_INTD_CFG_INTD_CFG 0x0004508000 0x0004509000 4 KB
CSI_RX_IF1_RX_SHIM_VBUSP_MMR_CSI2RXIF 0x0004510000 0x0004511000 4 KB
CSI_RX_IF1_VBUS2APB_WRAP_VBUSP_APB_CSI2RX 0x0004514000 0x0004515000 4 KB
CSI_RX_IF1_CP_INTD_CFG_INTD_CFG 0x0004518000 0x0004519000 4 KB
CSI_RX_IF2_RX_SHIM_VBUSP_MMR_CSI2RXIF 0x0004520000 0x0004521000 4 KB
CSI_RX_IF2_VBUS2APB_WRAP_VBUSP_APB_CSI2RX 0x0004524000 0x0004525000 4 KB
CSI_RX_IF2_CP_INTD_CFG_INTD_CFG 0x0004528000 0x0004529000 4 KB
DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX 0x0004580000 0x0004581000 4 KB
DPHY_RX0_MMR_SLV_K3_DPHY_WRAP 0x0004581000 0x0004581100 256 B
DPHY_RX1_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX 0x0004590000 0x0004591000 4 KB
DPHY_RX1_MMR_SLV_K3_DPHY_WRAP 0x0004591000 0x0004591100 256 B
DPHY_RX2_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX 0x00045A0000 0x00045A1000 4 KB
DPHY_RX2_MMR_SLV_K3_DPHY_WRAP 0x00045A1000 0x00045A1100 256 B
DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG 0x0004700000 0x0004700400 1 KB
DSS_DSI1_DSI_TOP_ECC_AGGR_SYS_CFG 0x0004701000 0x0004701400 1 KB
DSS_DSI0_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP 0x0004710000 0x0004710100 256 B
DSS_DSI1_DSI_WRAP_MMR_VBUSP_CFG_DSI_WRAP 0x0004720000 0x0004720100 256 B
DSS_DSI0_DSI_TOP_VBUSP_CFG_DSI_0_DSI 0x0004800000 0x0004900000 1 MB
DSS_DSI1_DSI_TOP_VBUSP_CFG_DSI_0_DSI 0x0004900000 0x0004A00000 1 MB
DSS0_DISPC_0_COMMON_M 0x0004A00000 0x0004A10000 64 KB
DSS0_DISPC_0_COMMON_S0 0x0004A10000 0x0004A20000 64 KB
DSS0_VIDL1 0x0004A20000 0x0004A30000 64 KB
DSS0_VIDL2 0x0004A30000 0x0004A40000 64 KB
DSS0_VID1 0x0004A50000 0x0004A60000 64 KB
DSS0_VID2 0x0004A60000 0x0004A70000 64 KB
DSS0_OVR1 0x0004A70000 0x0004A80000 64 KB
DSS0_VP1 0x0004A80000 0x0004A90000 64 KB
DSS0_OVR2 0x0004A90000 0x0004AA0000 64 KB
DSS0_VP2 0x0004AA0000 0x0004AB0000 64 KB
DSS0_OVR3 0x0004AB0000 0x0004AC0000 64 KB
DSS0_VP3 0x0004AC0000 0x0004AD0000 64 KB
DSS0_OVR4 0x0004AD0000 0x0004AE0000 64 KB
DSS0_VP4 0x0004AE0000 0x0004AF0000 64 KB
DSS0_WB 0x0004AF0000 0x0004B00000 64 KB
DSS0_DISPC_0_COMMON_S1 0x0004B00000 0x0004B10000 64 KB
DSS0_DISPC_0_COMMON_S2 0x0004B10000 0x0004B20000 64 KB
SA2_UL0 0x0004E00000 0x0004E01000 4 KB
SA2_UL0_MMRA 0x0004E01000 0x0004E01200 512 B
SA2_UL0_EIP_76 0x0004E10000 0x0004E10080 128 B
SA2_UL0_EIP_29T2 0x0004E20000 0x0004E30000 64 KB
UFS0_SYSCFG_SS_CFG 0x0004E80000 0x0004E80100 256 B
UFS0_P2A_WRAP_CFG_VBP_UFSHCI 0x0004E84000 0x0004E86000 8 KB
DSS_EDP0_INTG_CFG_VP 0x0004F40000 0x0004F40100 256 B
DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB 0x0004F48000 0x0004F48100 256 B
MMCSD0_CTL_CFG 0x0004F80000 0x0004F81000 4 KB
MMCSD0_SS_CFG 0x0004F88000 0x0004F88400 1 KB
MMCSD1_CTL_CFG 0x0004FB0000 0x0004FB1000 4 KB
MMCSD1_SS_CFG 0x0004FB8000 0x0004FB8400 1 KB
WIZ16B8M4CT3_2_WIZ16B8M4CT3 0x0005020000 0x0005030000 64 KB
WIZ16B8M4CT3_4_WIZ16B8M4CT3 0x0005050000 0x0005060000 64 KB
WIZ16B8M4CT3_0_WIZ16B8M4CT3 0x0005060000 0x0005070000 64 KB
WIZ16B8M4CT3_1_WIZ16B8M4CT3 0x0005070000 0x0005080000 64 KB
ELM0 0x0005380000 0x0005381000 4 KB
GPMC0_CFG 0x0005390000 0x0005390400 1 KB
EFUSE0 0x00053F0000 0x00053F0100 256 B
R5FSS2_CORE0_ATCM 0x0005900000 0x0005910000 64 KB
R5FSS2_CORE0_BTCM 0x0005910000 0x0005920000 64 KB
R5FSS2_CORE1_ATCM 0x0005A00000 0x0005A08000 32 KB
R5FSS2_CORE1_BTCM 0x0005A10000 0x0005A18000 32 KB
R5FSS0_COMPARE_CFG 0x0005B00000 0x0005B00100 256 B
R5FSS0_CORE1_ECC_AGGR 0x0005B10000 0x0005B10400 1 KB
R5FSS1_COMPARE_CFG 0x0005B20000 0x0005B20100 256 B
R5FSS1_CORE1_ECC_AGGR 0x0005B30000 0x0005B30400 1 KB
R5FSS2_COMPARE_CFG 0x0005B40000 0x0005B40100 256 B
R5FSS2_CORE1_ECC_AGGR 0x0005B50000 0x0005B50400 1 KB
R5FSS0_CORE0_ATCM 0x0005C00000 0x0005C10000 64 KB
R5FSS0_CORE0_BTCM 0x0005C10000 0x0005C20000 64 KB
R5FSS0_CORE1_ATCM 0x0005D00000 0x0005D08000 32 KB
R5FSS0_CORE1_BTCM 0x0005D10000 0x0005D18000 32 KB
R5FSS1_CORE0_ATCM 0x0005E00000 0x0005E10000 64 KB
R5FSS1_CORE0_BTCM 0x0005E10000 0x0005E20000 64 KB
R5FSS1_CORE1_ATCM 0x0005F00000 0x0005F08000 32 KB
R5FSS1_CORE1_BTCM 0x0005F10000 0x0005F18000 32 KB
USB0_VBP2APB_WRAP_CONTROLLER_VBP_CORE_ADDR_MAP 0x0006000000 0x0006400000 4 MB
DEBUGSS0_SYS 0x0008000000 0x0008001000 4 KB
CCDEBUGSS1_SYS 0x0008004000 0x0008005000 4 KB
CCDEBUGSS0_SYS 0x0008008000 0x0008009000 4 KB
CCDEBUGSS2_SYS 0x000800C000 0x000800D000 4 KB
STM0_STIMULUS 0x0009000000 0x000A000000 16 MB
DSS_EDP0_V2A_CORE_VP_REGS_APB 0x000A000000 0x000A040000 256 KB
CPSW_9XUSSM0_CPSW_NUSS_VBUSP 0x000C000000 0x000C200000 2 MB
CPSW1_NUSS 0x000C200000 0x000C400000 2 MB
PCIE0_CORE_DBN_CFG_PCIE_CORE 0x000D000000 0x000D800000 8 MB
PCIE1_CORE_DBN_CFG_PCIE_CORE 0x000D800000 0x000E000000 8 MB
PCIE2_CORE_DBN_CFG_PCIE_CORE 0x000E000000 0x000E800000 8 MB
PCIE3_CORE_DBN_CFG_PCIE_CORE 0x000E800000 0x000F000000 8 MB
DMPAC0_DMPAC_REGS_DMPAC_REGS_CFG_IP_MMRS 0x000F400000 0x000F400400 1 KB
DMPAC0_CP_INTD_CFG_INTD_CFG 0x000F401000 0x000F402000 4 KB
DMPAC0_HTS_S_VBUSP 0x000F408000 0x000F410000 32 KB
DMPAC0_CTSET2_WRAP_CFG_CTSET2_CFG 0x000F420000 0x000F422000 8 KB
DMPAC0_DMPAC_FOCO_0_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS 0x000F424000 0x000F424040 64 B
DMPAC0_DMPAC_FOCO_0_CFG_SLV_VPAC_FOCO_LSE_CFG_VP 0x000F424200 0x000F424400 512 B
DMPAC0_DMPAC_FOCO_1_CFG_SLV_DMPAC_FOCO_CORE_FOCO_REGS_CFG_IP_MMRS 0x000F428000 0x000F428040 64 B
DMPAC0_DMPAC_FOCO_1_CFG_SLV_VPAC_FOCO_LSE_CFG_VP 0x000F428200 0x000F428400 512 B
DMPAC0_PAR_DOF_CFG_VP_MMR_VBUSP_DOFCORE 0x000F480000 0x000F481000 4 KB
DMPAC0_PAR_DOF_CFG_VP_MEM_MMRRAM_VBUSP_MMR_RAM 0x000F4C0000 0x000F500000 256 KB
DMPAC0_PAR_PAR_SDE_S_VBUSP_MMR_VBUSP_MMR 0x000F500000 0x000F501000 4 KB
DMPAC0_PAR_PAR_SDE_S_VBUSP_MEM_MMRRAM_VBUSP_MMR_RAM 0x000F540000 0x000F580000 256 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU 0x000F600000 0x000F604000 16 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_SET 0x000F604000 0x000F608000 16 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE 0x000F608000 0x000F610000 32 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT 0x000F640000 0x000F660000 128 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHRT 0x000F660000 0x000F680000 128 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHATOMIC_DEBUG 0x000F680000 0x000F6A0000 128 KB
DMPAC0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CAUSE 0x000F6E0000 0x000F700000 128 KB
PCIE0_DAT0 0x0010000000 0x0018000000 128 MB
PCIE1_DAT0 0x0018000000 0x0020000000 128 MB
GPMC0_DATA 0x0020000000 0x0028000000 128 MB
NAVSS0_MSRAM0_SLV_RAM 0x0030000000 0x0030010000 64 KB
NAVSS0_MODSS_INTA0_CFG 0x0030800000 0x0030800020 32 B
NAVSS0_MODSS_INTA1_CFG 0x0030801000 0x0030801020 32 B
NAVSS0_UDMASS_INTA0_CFG 0x0030802000 0x0030802020 32 B
NAVSS0_UDMASS_INTA0_CFG_UNMAP 0x0030880000 0x0030890000 64 KB
NAVSS0_MODSS_INTA0_CFG_IMAP 0x0030900000 0x0030902000 8 KB
NAVSS0_MODSS_INTA1_CFG_IMAP 0x0030908000 0x003090A000 8 KB
NAVSS0_UDMASS_INTA0_IMAP 0x0030940000 0x0030950000 64 KB
NAVSS0_NAV_DDR0_VIRTID_CFG_MMRS 0x0030A02000 0x0030A02100 256 B
NAVSS0_NAV_DDR1_VIRTID_CFG_MMRS 0x0030A03000 0x0030A03100 256 B
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN 0x0030B00000 0x0030B20000 128 KB
NAVSS0_UDMASS_UDMAP0_CFG_RCHAN 0x0030C00000 0x0030C08000 32 KB
NAVSS0_UDMASS_UDMAP0_CFG_RFLOW 0x0030D00000 0x0030D04000 16 KB
NAVSS0_SPINLOCK 0x0030E00000 0x0030E08000 32 KB
NAVSS0_TIMERMGR0_CFG_CONFIG 0x0030E80000 0x0030E80200 512 B
NAVSS0_TIMERMGR1_CFG_CONFIG 0x0030E81000 0x0030E81200 512 B
NAVSS0_TIMERMGR0_CFG_OES 0x0030F00000 0x0030F01000 4 KB
NAVSS0_TIMERMGR1_CFG_OES 0x0030F01000 0x0030F02000 4 KB
NAVSS0_IO_PVU0_CFG_MMRS 0x0030F80000 0x0030F81000 4 KB
NAVSS0_IO_PVU1_CFG_MMRS 0x0030F81000 0x0030F82000 4 KB
NAVSS0_PVU0_SRC_TOG_CFG 0x0030F90000 0x0030F90400 1 KB
NAVSS0_PVU0_CFG_TOG_CFG 0x0030F91000 0x0030F91400 1 KB
NAVSS0_ECCAGGR0_REGS 0x0031000000 0x0031000400 1 KB
NAVSS0_UDMASS_ECCAGGR0_CFG_REGS 0x0031001000 0x0031001400 1 KB
NAVSS0_VIRTSS_ECCAGGR_CFG 0x0031002000 0x0031002400 1 KB
NAVSS0_UDMASS_INTA0_CFG_GCNTCFG 0x0031040000 0x0031044000 16 KB
NAVSS0_UDMASS_RINGACC0_CFG 0x0031080000 0x00310C0000 256 KB
NAVSS0_CFG 0x00310C0000 0x00310C0100 256 B
NAVSS0_CPTS 0x00310D0000 0x00310D0400 1 KB
NAVSS0_INTR0_INTR_ROUTER_CFG 0x00310E0000 0x00310E4000 16 KB
NAVSS0_UDMASS_INTA0_CFG_L2G 0x0031100000 0x0031102000 8 KB
NAVSS0_UDMASS_INTA0_CFG_MCAST 0x0031110000 0x0031114000 16 KB
NAVSS0_PROXY0_CFG_BUF_CFG 0x0031120000 0x0031120100 256 B
NAVSS0_PROXY_BUF 0x0031130000 0x0031134000 16 KB
NAVSS0_SEC_PROXY0_CFG_MMRS 0x0031140000 0x0031140100 256 B
NAVSS0_UDMASS_UDMAP0_CFG 0x0031150000 0x0031150100 256 B
NAVSS0_UDMASS_RINGACC0_GCFG 0x0031160000 0x0031160400 1 KB
NAVSS0_PSILSS0_CFG_MMRS 0x0031170000 0x0031171000 4 KB
NAVSS0_BCDMA0_CFG_GCFG 0x00311A0000 0x00311A0100 256 B
NAVSS0_MCRC 0x0031F70000 0x0031F71000 4 KB
NAVSS0_UDMASS_PSILCFG0_CFG_PROXY 0x0031F78000 0x0031F78200 512 B
NAVSS0_MAILBOX_REGS0 0x0031F80000 0x0031F80200 512 B
NAVSS0_MAILBOX_REGS1 0x0031F81000 0x0031F81200 512 B
NAVSS0_MAILBOX_REGS2 0x0031F82000 0x0031F82200 512 B
NAVSS0_MAILBOX_REGS3 0x0031F83000 0x0031F83200 512 B
NAVSS0_MAILBOX_REGS4 0x0031F84000 0x0031F84200 512 B
NAVSS0_MAILBOX_REGS5 0x0031F85000 0x0031F85200 512 B
NAVSS0_MAILBOX_REGS6 0x0031F86000 0x0031F86200 512 B
NAVSS0_MAILBOX_REGS7 0x0031F87000 0x0031F87200 512 B
NAVSS0_MAILBOX_REGS8 0x0031F88000 0x0031F88200 512 B
NAVSS0_MAILBOX_REGS9 0x0031F89000 0x0031F89200 512 B
NAVSS0_MAILBOX_REGS10 0x0031F8A000 0x0031F8A200 512 B
NAVSS0_MAILBOX_REGS11 0x0031F8B000 0x0031F8B200 512 B
NAVSS0_MAILBOX1_REGS0 0x0031F90000 0x0031F90200 512 B
NAVSS0_MAILBOX1_REGS1 0x0031F91000 0x0031F91200 512 B
NAVSS0_MAILBOX1_REGS2 0x0031F92000 0x0031F92200 512 B
NAVSS0_MAILBOX1_REGS3 0x0031F93000 0x0031F93200 512 B
NAVSS0_MAILBOX1_REGS4 0x0031F94000 0x0031F94200 512 B
NAVSS0_MAILBOX1_REGS5 0x0031F95000 0x0031F95200 512 B
NAVSS0_MAILBOX1_REGS6 0x0031F96000 0x0031F96200 512 B
NAVSS0_MAILBOX1_REGS7 0x0031F97000 0x0031F97200 512 B
NAVSS0_MAILBOX1_REGS8 0x0031F98000 0x0031F98200 512 B
NAVSS0_MAILBOX1_REGS9 0x0031F99000 0x0031F99200 512 B
NAVSS0_MAILBOX1_REGS10 0x0031F9A000 0x0031F9A200 512 B
NAVSS0_MAILBOX1_REGS11 0x0031F9B000 0x0031F9B200 512 B
NAVSS0_UDMASS_RINGACC0_CFG_MON 0x0032000000 0x0032020000 128 KB
NAVSS0_TIMERMGR0_CFG_TIMERS 0x0032200000 0x0032240000 256 KB
NAVSS0_TIMERMGR1_CFG_TIMERS 0x0032240000 0x0032280000 256 KB
NAVSS0_SEC_PROXY0_CFG_RT 0x0032400000 0x0032600000 2 MB
NAVSS0_SEC_PROXY0_CFG_SCFG 0x0032800000 0x0032A00000 2 MB
NAVSS0_SEC_PROXY0_SRC_TARGET_DATA 0x0032C00000 0x0032E00000 2 MB
NAVSS0_PROXY_TARGET0_DATA 0x0033000000 0x0033040000 256 KB
NAVSS0_PROXY0_BUF_CFG 0x0033400000 0x0033440000 256 KB
NAVSS0_UDMASS_INTA0_CFG_GCNTRTI 0x0033800000 0x0033A00000 2 MB
NAVSS0_MODSS_INTA0_CFG_INTR 0x0033C00000 0x0033C40000 256 KB
NAVSS0_MODSS_INTA1_CFG_INTR 0x0033C40000 0x0033C80000 256 KB
NAVSS0_UDMASS_INTA0_CFG_INTR 0x0033D00000 0x0033E00000 1 MB
NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT 0x0034000000 0x0034080000 512 KB
NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT 0x0035000000 0x0035200000 2 MB
NAVSS0_BCDMA0_CFG_TCHAN 0x0035840000 0x0035841000 4 KB
NAVSS0_BCDMA0_CFG_RCHAN 0x0035880000 0x0035882000 8 KB
NAVSS0_BCDMA0_CFG_RING 0x0035900000 0x0035904000 16 KB
NAVSS0_BCDMA0_CFG_TCHANRT 0x0035C00000 0x0035C10000 64 KB
NAVSS0_BCDMA0_CFG_RCHANRT 0x0035D00000 0x0035D20000 128 KB
NAVSS0_BCDMA0_CFG_RINGRT 0x0035E00000 0x0035E80000 512 KB
NAVSS0_IO_PVU0_CFG_TLBIF_TLB 0x0036000000 0x0036040000 256 KB
NAVSS0_IO_PVU1_CFG_TLBIF_TLB 0x0036040000 0x0036080000 256 KB
NAVSS0_UDMASS_RINGACC0_SRC_FIFOS 0x0038000000 0x0038400000 4 MB
NAVSS0_UDMASS_RINGACC0_CFG_RT 0x003C000000 0x003C400000 4 MB
MCU_MCAN0_ECC_AGGR 0x0040700000 0x0040700400 1 KB
MCU_MCAN1_ECC_AGGR 0x0040701000 0x0040701400 1 KB
MCU_ADC12FCC0_ECC 0x0040707000 0x0040707400 1 KB
MCU_ADC12FCC1_ECC 0x0040708000 0x0040708400 1 KB
MCU_CPSW0_ECC 0x0040709000 0x0040709400 1 KB
MCU_MSRAM_1MB0_ECC_AGGR_REGS 0x004070B000 0x004070B400 1 KB
MCU_I3C0_P_ECC_AGGR_CFG 0x0040720000 0x0040720400 1 KB
MCU_I3C0_S_ECC_AGGR_CFG 0x0040721000 0x0040721400 1 KB
MCU_I3C1_P_ECC_AGGR_CFG 0x0040722000 0x0040722400 1 KB
MCU_I3C1_S_ECC_AGGR_CFG 0x0040723000 0x0040723400 1 KB
MCU_VDC_INFRA_VBUSP_32B_SRC_SAFEG0_CFG 0x0040731000 0x0040731400 1 KB
MCU_VDC_SOC_FW_VBUSP_32B_SRC_SAFEG1_CFG 0x0040732000 0x0040732400 1 KB
WKUP_ECC_AGGR0_REGS 0x0042410000 0x0042410400 1 KB
WKUP_VTM0_ECCAGGR_CFG 0x0042810000 0x0042810400 1 KB
WKUP_VDC_INFRA_VBUSP_32B_SRC_SAFEG0_CFG 0x0042900000 0x0042900400 1 KB
MAIN_CBASS0_FW 0x0045000000 0x0045008000 32 KB
CBASS_INFRA_NON_SAFE0_FW 0x0045010000 0x0045020000 64 KB
COMPUTE_CLUSTERHP0_VBUSP_CPAC0_FW_CPAC0_FW 0x0045040400 0x0045040800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CPAC1_FW_CPAC1_FW 0x0045040C00 0x0045041000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW4_FW_CPAC4_L2PIPE_FW 0x0045042000 0x0045042400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW4_FW_CPAC4_MDMA_FW 0x0045042400 0x0045042800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW5_FW_CPAC5_L2PIPE_FW 0x0045042800 0x0045042C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW5_FW_CPAC5_MDMA_FW 0x0045042C00 0x0045043000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW6_FW_CPAC6_L2PIPE_FW 0x0045043000 0x0045043400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW6_FW_CPAC6_MDMA_FW 0x0045043400 0x0045043800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW7_FW_CPAC7_L2PIPE_FW 0x0045043800 0x0045043C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW7_FW_CPAC7_MDMA_FW 0x0045043C00 0x0045044000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU0_FW_DRU_FW 0x0045047000 0x0045047400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU0_MMR_FW_DRU_MMR_FW 0x0045048000 0x0045050000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU4_FW_DRU_FW 0x0045050000 0x0045050400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU5_FW_DRU_FW 0x0045050400 0x0045050800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU6_FW_DRU_FW 0x0045050800 0x0045050C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU7_FW_DRU_FW 0x0045050C00 0x0045051000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU4_MMR_FW_DRU_MMR_FW 0x0045058000 0x0045060000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU5_MMR_FW_DRU_MMR_FW 0x0045060000 0x0045068000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU6_MMR_FW_DRU_MMR_FW 0x0045068000 0x0045070000 32 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU7_MMR_FW_DRU_MMR_FW 0x0045070000 0x0045078000 32 KB
CBASS_IPPHY_SAFE0_FW 0x0045200000 0x0045220000 128 KB
CBASS_IPPHY0_FW 0x0045220000 0x0045240000 128 KB
CBASS_RC0_FW 0x0045240000 0x0045244000 16 KB
CBASS_RC_CFG0_FW 0x0045258000 0x0045258800 2 KB
CBASS_CSI0_FW 0x0045260000 0x0045268000 32 KB
CBASS_DATADEBUG0_FW 0x0045268000 0x0045270000 32 KB
CBASS_HC2_0_FW 0x0045278000 0x0045280000 32 KB
CBASS_HC_CFG0_FW 0x0045280000 0x0045288000 32 KB
CBASS_AC_NONSAFE0_FW 0x0045290000 0x0045290800 2 KB
CBASS_AC_CFG_NONSAFE0_FW 0x00452A0000 0x00452B0000 64 KB
AM_PULSAR0_SLV_CBASS0_FW 0x00452B0000 0x00452C0000 64 KB
CBASS_AC_CFG0_FW 0x00452C0000 0x00452C8000 32 KB
AM_PULSAR0_MEM_CBASS0_FW 0x00452D0000 0x00452D0400 1 KB
AM_PULSAR1_MEM_CBASS0_FW 0x00452E0000 0x00452E2000 8 KB
NAVSS0_UDMASS_DMSC_FW 0x0045400000 0x0045480000 512 KB
NAVSS0_MODSS_DMSC_FW 0x0045480000 0x00454C0000 256 KB
NAVSS0_VIRTSS_DMSC_FW 0x0045500000 0x0045508000 32 KB
DMPAC0_CFG_DMSC_FW 0x00455D8000 0x00455DC000 16 KB
DMPAC0_SL2_DMSC_FW 0x00455E0000 0x00455E1000 4 KB
VPAC0_DMSC_VPAC_SCRPFW 0x00455E8000 0x00455EC000 16 KB
VPAC1_DMSC_VPAC_SCRPFW 0x00455EC000 0x00455F0000 16 KB
VPAC0_DMSC_VPAC_SCRMFW 0x00455F0000 0x00455F1000 4 KB
VPAC1_DMSC_VPAC_SCRMFW 0x00455F1000 0x00455F2000 4 KB
COMPUTE_CLUSTERHP0_DMSC_PRIVID 0x0045830000 0x0045834000 16 KB
NAVSS0_MODSS_DMSC_ISC 0x0045840000 0x0045840800 2 KB
DMPAC0_SL2_DMSC_ISC 0x0045858000 0x004585C000 16 KB
VPAC0_DMSC_VPAC_SCRMISC 0x0045860000 0x0045862000 8 KB
VPAC1_DMSC_VPAC_SCRMISC 0x0045862000 0x0045864000 8 KB
NAVSS0_UDMASS_RINGACC0_ISC 0x0045870000 0x0045878000 32 KB
CBASS_IPPHY_SAFE0_ISC 0x0045878000 0x0045879000 4 KB
CBASS_RC0_ISC 0x0045880000 0x0045890000 64 KB
CBASS_HC2_0_ISC 0x0045898000 0x00458A0000 32 KB
CBASS_DATADEBUG0_ISC 0x00458A0000 0x00458A0800 2 KB
CBASS_AC_NONSAFE0_ISC 0x00458C0000 0x00458C8000 32 KB
AM_PULSAR0_MEM_CBASS0_ISC 0x00458C8000 0x00458C9000 4 KB
AM_PULSAR1_PERIPH_SWITCH_CBASS0_ISC 0x00458CA000 0x00458CC000 8 KB
NAVSS0_UDMASS_DMSC_ISC 0x00458D0000 0x00458D0400 1 KB
AM_PULSAR1_MEM_CBASS0_ISC 0x00458D8000 0x00458DA000 8 KB
NAVSS0_CRED 0x00458E8000 0x00458E8400 1 KB
COMPUTE_CLUSTERHP0_DMSC_EMULATION 0x0045900000 0x0045904000 16 KB
SEC_MMR0_DBG_CTRL 0x0045944000 0x0045948000 16 KB
COMPUTE_CLUSTERHP0_DMSC_BOOT 0x0045A00000 0x0045A10000 64 KB
SEC_MMR0_BOOT_CTRL 0x0045A40000 0x0045A44000 16 KB
CBASS_AC_NONSAFE0_GLB 0x0045B08000 0x0045B08400 1 KB
NAVSS0_MODSS_DMSC_GLB 0x0045B0A000 0x0045B0A400 1 KB
NAVSS0_UDMASS_DMSC_GLB 0x0045B0B000 0x0045B0B400 1 KB
NAVSS0_VIRTSS_DMSC_GLB 0x0045B0B800 0x0045B0BC00 1 KB
MAIN_CBASS0_GLB 0x0045B0C000 0x0045B0C400 1 KB
DMPAC0_CFG_DMSC_GLB 0x0045B0D000 0x0045B0D400 1 KB
DMPAC0_SL2_DMSC_GLB 0x0045B0D400 0x0045B0D800 1 KB
VPAC0_DMSC_VPAC_SCRMGLB 0x0045B0D800 0x0045B0DC00 1 KB
VPAC0_DMSC_VPAC_SCRPGLB 0x0045B0DC00 0x0045B0E000 1 KB
VPAC1_DMSC_VPAC_SCRMGLB 0x0045B0E000 0x0045B0E400 1 KB
VPAC1_DMSC_VPAC_SCRPGLB 0x0045B0E400 0x0045B0E800 1 KB
CBASS_CSI0_GLB 0x0045B20400 0x0045B20800 1 KB
CBASS_DATADEBUG0_GLB 0x0045B20800 0x0045B20C00 1 KB
CBASS_HC_CFG0_GLB 0x0045B21000 0x0045B21400 1 KB
CBASS_IPPHY0_GLB 0x0045B21400 0x0045B21800 1 KB
CBASS_RC0_GLB 0x0045B22000 0x0045B22400 1 KB
CBASS_RC_CFG0_GLB 0x0045B22400 0x0045B22800 1 KB
CBASS_HC2_0_GLB 0x0045B22800 0x0045B22C00 1 KB
CBASS_AC_CFG0_GLB 0x0045B22C00 0x0045B23000 1 KB
AM_PULSAR0_MEM_CBASS0_GLB 0x0045B23000 0x0045B23400 1 KB
AM_PULSAR0_SLV_CBASS0_GLB 0x0045B23400 0x0045B23800 1 KB
AM_PULSAR1_MEM_CBASS0_GLB 0x0045B23800 0x0045B23C00 1 KB
AM_PULSAR1_PERIPH_SWITCH_CBASS0_GLB 0x0045B23C00 0x0045B24000 1 KB
CBASS_INFRA_NON_SAFE0_GLB 0x0045B24000 0x0045B24400 1 KB
CBASS_IPPHY_SAFE0_GLB 0x0045B24400 0x0045B24800 1 KB
CBASS_AC_CFG_NONSAFE0_GLB 0x0045B25000 0x0045B25400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CPAC0_FW_CPAC0_FW_GLB 0x0045BC0400 0x0045BC0800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CPAC1_FW_CPAC1_FW_GLB 0x0045BC0C00 0x0045BC1000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW4_FW_CPAC4_L2PIPE_FW_GLB 0x0045BC2000 0x0045BC2400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW4_FW_CPAC4_MDMA_FW_GLB 0x0045BC2400 0x0045BC2800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW5_FW_CPAC5_L2PIPE_FW_GLB 0x0045BC2800 0x0045BC2C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW5_FW_CPAC5_MDMA_FW_GLB 0x0045BC2C00 0x0045BC3000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW6_FW_CPAC6_L2PIPE_FW_GLB 0x0045BC3000 0x0045BC3400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW6_FW_CPAC6_MDMA_FW_GLB 0x0045BC3400 0x0045BC3800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW7_FW_CPAC7_L2PIPE_FW_GLB 0x0045BC3800 0x0045BC3C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_AW7_FW_CPAC7_MDMA_FW_GLB 0x0045BC3C00 0x0045BC4000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU0_FW_DRU_FW_GLB 0x0045BC7000 0x0045BC7400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU0_MMR_FW_DRU_MMR_FW_GLB 0x0045BC8000 0x0045BC8400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU4_FW_DRU_FW_GLB 0x0045BD0000 0x0045BD0400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU5_FW_DRU_FW_GLB 0x0045BD0400 0x0045BD0800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU6_FW_DRU_FW_GLB 0x0045BD0800 0x0045BD0C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU7_FW_DRU_FW_GLB 0x0045BD0C00 0x0045BD1000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU4_MMR_FW_DRU_MMR_FW_GLB 0x0045BD8000 0x0045BD8400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU5_MMR_FW_DRU_MMR_FW_GLB 0x0045BE0000 0x0045BE0400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU6_MMR_FW_DRU_MMR_FW_GLB 0x0045BE8000 0x0045BE8400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DRU7_MMR_FW_DRU_MMR_FW_GLB 0x0045BF0000 0x0045BF0400 1 KB
NAVSS0_MODSS_DMSC_QOS 0x0045D40000 0x0045D40800 2 KB
CBASS_IPPHY_SAFE0_QOS 0x0045D78000 0x0045D79000 4 KB
CBASS_RC0_QOS 0x0045D80000 0x0045D88000 32 KB
CBASS_HC2_0_QOS 0x0045D98000 0x0045DA0000 32 KB
CBASS_DATADEBUG0_QOS 0x0045DA0000 0x0045DA0800 2 KB
AM_PULSAR1_MEM_CBASS0_QOS 0x0045DA8000 0x0045DAA000 8 KB
CBASS_AC_NONSAFE0_QOS 0x0045DC0000 0x0045DC8000 32 KB
AM_PULSAR0_MEM_CBASS0_QOS 0x0045DC8000 0x0045DC9000 4 KB
AM_PULSAR1_PERIPH_SWITCH_CBASS0_QOS 0x0045DCA000 0x0045DCC000 8 KB
MCUM_MCU_ECC_AGGR0_REGS 0x0047200000 0x0047200400 1 KB
IAM_CNM_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_BW_LIMITER0_REGS 0x0048000000 0x0048001000 4 KB
IAM_CNM_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_BW_LIMITER0_REGS 0x0048001000 0x0048002000 4 KB
IGPU_MAIN_0_M0_VBUSM_R_ASYNC_BW_LIMITER0_REGS 0x0048006000 0x0048007000 4 KB
IGPU_MAIN_0_M0_VBUSM_W_ASYNC_BW_LIMITER0_REGS 0x0048007000 0x0048008000 4 KB
IAM_CNM_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_BW_LIMITER0_REGS 0x004800E000 0x004800F000 4 KB
IAM_CNM_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_BW_LIMITER0_REGS 0x004800F000 0x0048010000 4 KB
NAVSS0_SRAM0 0x0060000000 0x0080000000 512 MB
NAVSS0_SRAM1 0x0060000000 0x0080000000 512 MB
COMPUTE_CLUSTERHP0_CPU0 0x0060000000 0x0061000000 16 MB
COMPUTE_CLUSTERHP0_CPU1 0x0061000000 0x0062000000 16 MB
COMPUTE_CLUSTERHP0_CPU2 0x0062000000 0x0063000000 16 MB
COMPUTE_CLUSTERHP0_CPU3 0x0063000000 0x0064000000 16 MB
COMPUTE_CLUSTERHP0_CPU4 0x0064000000 0x0065000000 16 MB
COMPUTE_CLUSTERHP0_CPU5 0x0065000000 0x0066000000 16 MB
COMPUTE_CLUSTERHP0_CPU6 0x0066000000 0x0067000000 16 MB
COMPUTE_CLUSTERHP0_CPU7 0x0067000000 0x0068000000 16 MB
COMPUTE_CLUSTERHP0_AW4_SRAM 0x0068000000 0x0068800000 8 MB
COMPUTE_CLUSTERHP0_AW4_MSMC1_CFGS0 0x0068800000 0x0069800000 16 MB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU 0x0068A00000 0x0068A04000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU 0x0068A00000 0x0068A04000 16 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_SET 0x0068A04000 0x0068A08000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_SET 0x0068A04000 0x0068A08000 16 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_QUEUE 0x0068A08000 0x0068A0A000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_QUEUE 0x0068A08000 0x0068A0A000 8 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_MMU 0x0068A0A000 0x0068A0C000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_MMU 0x0068A0A000 0x0068A0C000 8 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_UTLB 0x0068A0C000 0x0068A10000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_UTLB 0x0068A0C000 0x0068A10000 16 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_MEM_ATT0 0x0068A10000 0x0068A20000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_MEM_ATT0 0x0068A10000 0x0068A20000 64 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_MEM_ATT1 0x0068A20000 0x0068A30000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_MEM_ATT1 0x0068A20000 0x0068A30000 64 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_MEM_ATT2 0x0068A30000 0x0068A40000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_MEM_ATT2 0x0068A30000 0x0068A40000 64 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_CHNRT 0x0068A40000 0x0068A60000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_CHNRT 0x0068A40000 0x0068A60000 128 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_CHRT 0x0068A60000 0x0068A80000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_CHRT 0x0068A60000 0x0068A80000 128 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_CHATOMIC_DEBUG 0x0068A80000 0x0068AA0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_CHATOMIC_DEBUG 0x0068A80000 0x0068AA0000 128 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_CHCORE 0x0068AA0000 0x0068AC0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_CHCORE 0x0068AA0000 0x0068AC0000 128 KB
COMPUTE_CLUSTERHP0_AW4_DRU_DRU_CAUSE 0x0068AE0000 0x0068B00000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU4_MMR_CFG_DRU_CAUSE 0x0068AE0000 0x0068B00000 128 KB
COMPUTE_CLUSTERHP0_AW5_SRAM 0x0069000000 0x0069800000 8 MB
COMPUTE_CLUSTERHP0_AW5_MSMC1_CFGS0 0x0069800000 0x006A800000 16 MB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU 0x0069A00000 0x0069A04000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU 0x0069A00000 0x0069A04000 16 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_SET 0x0069A04000 0x0069A08000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_SET 0x0069A04000 0x0069A08000 16 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_QUEUE 0x0069A08000 0x0069A0A000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_QUEUE 0x0069A08000 0x0069A0A000 8 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_MMU 0x0069A0A000 0x0069A0C000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_MMU 0x0069A0A000 0x0069A0C000 8 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_UTLB 0x0069A0C000 0x0069A10000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_UTLB 0x0069A0C000 0x0069A10000 16 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_MEM_ATT0 0x0069A10000 0x0069A20000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_MEM_ATT0 0x0069A10000 0x0069A20000 64 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_MEM_ATT1 0x0069A20000 0x0069A30000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_MEM_ATT1 0x0069A20000 0x0069A30000 64 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_MEM_ATT2 0x0069A30000 0x0069A40000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_MEM_ATT2 0x0069A30000 0x0069A40000 64 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_CHNRT 0x0069A40000 0x0069A60000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_CHNRT 0x0069A40000 0x0069A60000 128 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_CHRT 0x0069A60000 0x0069A80000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_CHRT 0x0069A60000 0x0069A80000 128 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_CHATOMIC_DEBUG 0x0069A80000 0x0069AA0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_CHATOMIC_DEBUG 0x0069A80000 0x0069AA0000 128 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_CHCORE 0x0069AA0000 0x0069AC0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_CHCORE 0x0069AA0000 0x0069AC0000 128 KB
COMPUTE_CLUSTERHP0_AW5_DRU_DRU_CAUSE 0x0069AE0000 0x0069B00000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU5_MMR_CFG_DRU_CAUSE 0x0069AE0000 0x0069B00000 128 KB
COMPUTE_CLUSTERHP0_AW6_SRAM 0x006A000000 0x006A800000 8 MB
COMPUTE_CLUSTERHP0_AW6_MSMC1_CFGS0 0x006A800000 0x006B800000 16 MB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU 0x006AA00000 0x006AA04000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU 0x006AA00000 0x006AA04000 16 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_SET 0x006AA04000 0x006AA08000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_SET 0x006AA04000 0x006AA08000 16 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_QUEUE 0x006AA08000 0x006AA0A000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_QUEUE 0x006AA08000 0x006AA0A000 8 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_MMU 0x006AA0A000 0x006AA0C000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_MMU 0x006AA0A000 0x006AA0C000 8 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_UTLB 0x006AA0C000 0x006AA10000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_UTLB 0x006AA0C000 0x006AA10000 16 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_MEM_ATT0 0x006AA10000 0x006AA20000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_MEM_ATT0 0x006AA10000 0x006AA20000 64 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_MEM_ATT1 0x006AA20000 0x006AA30000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_MEM_ATT1 0x006AA20000 0x006AA30000 64 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_MEM_ATT2 0x006AA30000 0x006AA40000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_MEM_ATT2 0x006AA30000 0x006AA40000 64 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_CHNRT 0x006AA40000 0x006AA60000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_CHNRT 0x006AA40000 0x006AA60000 128 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_CHRT 0x006AA60000 0x006AA80000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_CHRT 0x006AA60000 0x006AA80000 128 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_CHATOMIC_DEBUG 0x006AA80000 0x006AAA0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_CHATOMIC_DEBUG 0x006AA80000 0x006AAA0000 128 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_CHCORE 0x006AAA0000 0x006AAC0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_CHCORE 0x006AAA0000 0x006AAC0000 128 KB
COMPUTE_CLUSTERHP0_AW6_DRU_DRU_CAUSE 0x006AAE0000 0x006AB00000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU6_MMR_CFG_DRU_CAUSE 0x006AAE0000 0x006AB00000 128 KB
COMPUTE_CLUSTERHP0_AW7_SRAM 0x006B000000 0x006B800000 8 MB
COMPUTE_CLUSTERHP0_AW7_MSMC1_CFGS0 0x006B800000 0x006C800000 16 MB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU 0x006BA00000 0x006BA04000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU 0x006BA00000 0x006BA04000 16 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_SET 0x006BA04000 0x006BA08000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_SET 0x006BA04000 0x006BA08000 16 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_QUEUE 0x006BA08000 0x006BA0A000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_QUEUE 0x006BA08000 0x006BA0A000 8 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_MMU 0x006BA0A000 0x006BA0C000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_MMU 0x006BA0A000 0x006BA0C000 8 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_UTLB 0x006BA0C000 0x006BA10000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_UTLB 0x006BA0C000 0x006BA10000 16 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_MEM_ATT0 0x006BA10000 0x006BA20000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_MEM_ATT0 0x006BA10000 0x006BA20000 64 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_MEM_ATT1 0x006BA20000 0x006BA30000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_MEM_ATT1 0x006BA20000 0x006BA30000 64 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_MEM_ATT2 0x006BA30000 0x006BA40000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_MEM_ATT2 0x006BA30000 0x006BA40000 64 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_CHNRT 0x006BA40000 0x006BA60000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_CHNRT 0x006BA40000 0x006BA60000 128 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_CHRT 0x006BA60000 0x006BA80000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_CHRT 0x006BA60000 0x006BA80000 128 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_CHATOMIC_DEBUG 0x006BA80000 0x006BAA0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_CHATOMIC_DEBUG 0x006BA80000 0x006BAA0000 128 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_CHCORE 0x006BAA0000 0x006BAC0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_CHCORE 0x006BAA0000 0x006BAC0000 128 KB
COMPUTE_CLUSTERHP0_AW7_DRU_DRU_CAUSE 0x006BAE0000 0x006BB00000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU7_MMR_CFG_DRU_CAUSE 0x006BAE0000 0x006BB00000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU 0x006D000000 0x006D004000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_SET 0x006D004000 0x006D008000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_QUEUE 0x006D008000 0x006D00A000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_MMU 0x006D00A000 0x006D00C000 8 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_UTLB 0x006D00C000 0x006D010000 16 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_MEM_ATT0 0x006D010000 0x006D020000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_MEM_ATT1 0x006D020000 0x006D030000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_MEM_ATT2 0x006D030000 0x006D040000 64 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_CHNRT 0x006D040000 0x006D060000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_CHRT 0x006D060000 0x006D080000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_CHATOMIC_DEBUG 0x006D080000 0x006D0A0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_CHCORE 0x006D0A0000 0x006D0C0000 128 KB
COMPUTE_CLUSTERHP0_MMR_DRU0_MMR_CFG_DRU_CAUSE 0x006D0E0000 0x006D100000 128 KB
COMPUTE_CLUSTERHP0_MSMC_CFGS0 0x006E000000 0x006F000000 16 MB
COMPUTE_CLUSTERHP0_UNALLOCATED0 0x006F000000 0x0070000000 16 MB
COMPUTE_CLUSTERHP0_MSMC_SRAM 0x0070000000 0x0074000000 64 MB
COMPUTE_CLUSTERHP0_MSMC_ATOMIC_COUNTERS 0x0074000000 0x0078000000 64 MB
COMPUTE_CLUSTERHP0_CLEC 0x0078000000 0x0080000000 128 MB
NAVSS0_DDR0_MEM 0x0080000000 0x0100000000 2 GB
NAVSS0_DDR1_MEM 0x0080000000 0x0100000000 2 GB
NAVSS0_DDR0_MEM1 0x0800000000 0x1000000000 32 GB
NAVSS0_DDR1_MEM1 0x0800000000 0x1000000000 32 GB
PCIE0_DAT1 0x4000000000 0x4100000000 4 GB
PCIE1_DAT1 0x4100000000 0x4200000000 4 GB
PCIE2_DAT1 0x4200000000 0x4300000000 4 GB
PCIE3_DAT1 0x4300000000 0x4400000000 4 GB
PCIE2_DAT0 0x4400000000 0x4408000000 128 MB
PCIE3_DAT0 0x4410000000 0x4418000000 128 MB
NAVSS0_ALIAS64K_MCRC0_S_CFG_MCRC64 0x4A1F700000 0x4A1F710000 64 KB
NAVSS0_ALIAS64K_PSILCFG0_CFG_PROXY 0x4A1F780000 0x4A1F782000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS0 0x4A1F800000 0x4A1F802000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS1 0x4A1F810000 0x4A1F812000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS2 0x4A1F820000 0x4A1F822000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS3 0x4A1F830000 0x4A1F832000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS4 0x4A1F840000 0x4A1F842000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS5 0x4A1F850000 0x4A1F852000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS6 0x4A1F860000 0x4A1F862000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS7 0x4A1F870000 0x4A1F872000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS8 0x4A1F880000 0x4A1F882000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS9 0x4A1F890000 0x4A1F892000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS10 0x4A1F8A0000 0x4A1F8A2000 8 KB
NAVSS0_ALIAS64K_MAILBOX0_CFG_REGS11 0x4A1F8B0000 0x4A1F8B2000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS0 0x4A1F900000 0x4A1F902000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS1 0x4A1F910000 0x4A1F912000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS2 0x4A1F920000 0x4A1F922000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS3 0x4A1F930000 0x4A1F932000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS4 0x4A1F940000 0x4A1F942000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS5 0x4A1F950000 0x4A1F952000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS6 0x4A1F960000 0x4A1F962000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS7 0x4A1F970000 0x4A1F972000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS8 0x4A1F980000 0x4A1F982000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS9 0x4A1F990000 0x4A1F992000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS10 0x4A1F9A0000 0x4A1F9A2000 8 KB
NAVSS0_ALIAS64K_MAILBOX1_CFG_REGS11 0x4A1F9B0000 0x4A1F9B2000 8 KB
NAVSS0_ALIAS64K_RINGACC0_CFG_MON 0x4A20000000 0x4A20200000 2 MB
NAVSS0_ALIAS64K_TIMERMGR0_CFG_TIMERS 0x4A22000000 0x4A22400000 4 MB
NAVSS0_ALIAS64K_TIMERMGR1_CFG_TIMERS 0x4A22400000 0x4A22800000 4 MB
NAVSS0_ALIAS64K_SEC_PROXY0_CFG_RT 0x4A24000000 0x4A26000000 32 MB
NAVSS0_ALIAS64K_SEC_PROXY0_CFG_SCFG 0x4A28000000 0x4A2A000000 32 MB
NAVSS0_ALIAS64K_SEC_PROXY0_SRC_TARGET_DATA 0x4A2C000000 0x4A2E000000 32 MB
NAVSS0_ALIAS64K_PROXY0_SRC_TARGET0_DATA 0x4A30000000 0x4A30400000 4 MB
NAVSS0_ALIAS64K_PROXY0_CFG_BUF_CFG 0x4A34000000 0x4A34400000 4 MB
NAVSS0_ALIAS64K_UDMASS_INTA0_CFG_GCNTRTI 0x4A38000000 0x4A3A000000 32 MB
NAVSS0_ALIAS64K_MODSS_INTA0_CFG_INTR 0x4A3C000000 0x4A3C400000 4 MB
NAVSS0_ALIAS64K_MODSS_INTA1_CFG_INTR 0x4A3C400000 0x4A3C800000 4 MB
NAVSS0_ALIAS64K_UDMASS_INTA0_CFG_INTR 0x4A3D000000 0x4A3E000000 16 MB
NAVSS0_ALIAS64K_UDMAP0_CFG_RCHANRT 0x4A40000000 0x4A40800000 8 MB
NAVSS0_ALIAS64K_UDMAP0_CFG_TCHANRT 0x4A50000000 0x4A52000000 32 MB
NAVSS0_ALIAS64K_BCDMA0_CFG_TCHAN 0x4A58400000 0x4A58410000 64 KB
NAVSS0_ALIAS64K_BCDMA0_CFG_RCHAN 0x4A58800000 0x4A58820000 128 KB
NAVSS0_ALIAS64K_BCDMA0_CFG_RING 0x4A59000000 0x4A59040000 256 KB
NAVSS0_ALIAS64K_BCDMA0_CFG_TCHANRT 0x4A5C000000 0x4A5C100000 1 MB
NAVSS0_ALIAS64K_BCDMA0_CFG_RCHANRT 0x4A5D000000 0x4A5D200000 2 MB
NAVSS0_ALIAS64K_BCDMA0_CFG_RINGRT 0x4A5E000000 0x4A5E800000 8 MB
NAVSS0_ALIAS64K_IO_PVU0_CFG_TLBIF_TLB 0x4A60000000 0x4A60400000 4 MB
NAVSS0_ALIAS64K_IO_PVU1_CFG_TLBIF_TLB 0x4A60400000 0x4A60800000 4 MB
NAVSS0_ALIAS64K_RINGACC0_SRC_FIFOS 0x4A80000000 0x4A84000000 64 MB
NAVSS0_ALIAS64K_RINGACC0_CFG_RT 0x4AC0000000 0x4AC4000000 64 MB
NAVSS0_VIRT_ALIAS_0_MODSS_INTA0_CFG 0x4B00800000 0x4B00800020 32 B
NAVSS0_VIRT_ALIAS_0_MODSS_INTA1_CFG 0x4B00801000 0x4B00801020 32 B
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG 0x4B00802000 0x4B00802020 32 B
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_UNMAP 0x4B00880000 0x4B00890000 64 KB
NAVSS0_VIRT_ALIAS_0_MODSS_INTA0_CFG_IMAP 0x4B00900000 0x4B00902000 8 KB
NAVSS0_VIRT_ALIAS_0_MODSS_INTA1_CFG_IMAP 0x4B00908000 0x4B0090A000 8 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_IMAP 0x4B00940000 0x4B00950000 64 KB
NAVSS0_VIRT_ALIAS_0_NAV_DDR0_VIRTID_CFG_MMRS 0x4B00A02000 0x4B00A02100 256 B
NAVSS0_VIRT_ALIAS_0_NAV_DDR1_VIRTID_CFG_MMRS 0x4B00A03000 0x4B00A03100 256 B
NAVSS0_VIRT_ALIAS_0_UDMAP0_CFG_TCHAN 0x4B00B00000 0x4B00B20000 128 KB
NAVSS0_VIRT_ALIAS_0_UDMAP0_CFG_RCHAN 0x4B00C00000 0x4B00C08000 32 KB
NAVSS0_VIRT_ALIAS_0_UDMAP0_CFG_RFLOW 0x4B00D00000 0x4B00D04000 16 KB
NAVSS0_VIRT_ALIAS_0_SPINLOCK0_CFG 0x4B00E00000 0x4B00E08000 32 KB
NAVSS0_VIRT_ALIAS_0_TIMERMGR0_CFG_CONFIG 0x4B00E80000 0x4B00E80200 512 B
NAVSS0_VIRT_ALIAS_0_TIMERMGR1_CFG_CONFIG 0x4B00E81000 0x4B00E81200 512 B
NAVSS0_VIRT_ALIAS_0_TIMERMGR0_CFG_OES 0x4B00F00000 0x4B00F01000 4 KB
NAVSS0_VIRT_ALIAS_0_TIMERMGR1_CFG_OES 0x4B00F01000 0x4B00F02000 4 KB
NAVSS0_VIRT_ALIAS_0_IO_PVU0_CFG_MMRS 0x4B00F80000 0x4B00F81000 4 KB
NAVSS0_VIRT_ALIAS_0_IO_PVU1_CFG_MMRS 0x4B00F81000 0x4B00F82000 4 KB
NAVSS0_VIRT_ALIAS_0_PVU0_SRC_TOG_CFG 0x4B00F90000 0x4B00F90400 1 KB
NAVSS0_VIRT_ALIAS_0_PVU0_CFG_TOG_CFG 0x4B00F91000 0x4B00F91400 1 KB
NAVSS0_VIRT_ALIAS_0_ECCAGGR0 0x4B01000000 0x4B01000400 1 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_ECCAGGR_CFG 0x4B01001000 0x4B01001400 1 KB
NAVSS0_VIRT_ALIAS_0_VIRTSS_ECCAGGR_CFG 0x4B01002000 0x4B01002400 1 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_GCNTCFG 0x4B01040000 0x4B01044000 16 KB
NAVSS0_VIRT_ALIAS_0_RINGACC0_CFG 0x4B01080000 0x4B010C0000 256 KB
NAVSS0_VIRT_ALIAS_0_REGS0_CFG_MMRS 0x4B010C0000 0x4B010C0100 256 B
NAVSS0_VIRT_ALIAS_0_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B010D0000 0x4B010D0400 1 KB
NAVSS0_VIRT_ALIAS_0_INTR0_CFG_INTR_ROUTER_CFG 0x4B010E0000 0x4B010E4000 16 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_L2G 0x4B01100000 0x4B01102000 8 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_MCAST 0x4B01110000 0x4B01114000 16 KB
NAVSS0_VIRT_ALIAS_0_PROXY0_CFG_BUF_CFG_GCFG 0x4B01120000 0x4B01120100 256 B
NAVSS0_VIRT_ALIAS_0_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B01130000 0x4B01134000 16 KB
NAVSS0_VIRT_ALIAS_0_SEC_PROXY0_CFG_MMRS 0x4B01140000 0x4B01140100 256 B
NAVSS0_VIRT_ALIAS_0_UDMAP0_CFG_GCFG 0x4B01150000 0x4B01150100 256 B
NAVSS0_VIRT_ALIAS_0_RINGACC0_CFG_GCFG 0x4B01160000 0x4B01160400 1 KB
NAVSS0_VIRT_ALIAS_0_PSILSS0_CFG_MMRS 0x4B01170000 0x4B01171000 4 KB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_GCFG 0x4B011A0000 0x4B011A0100 256 B
NAVSS0_VIRT_ALIAS_0_MCRC0_S_CFG_MCRC64 0x4B01F70000 0x4B01F71000 4 KB
NAVSS0_VIRT_ALIAS_0_PSILCFG0_CFG_PROXY 0x4B01F78000 0x4B01F78200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS0 0x4B01F80000 0x4B01F80200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS1 0x4B01F81000 0x4B01F81200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS2 0x4B01F82000 0x4B01F82200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS3 0x4B01F83000 0x4B01F83200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS4 0x4B01F84000 0x4B01F84200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS5 0x4B01F85000 0x4B01F85200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS6 0x4B01F86000 0x4B01F86200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS7 0x4B01F87000 0x4B01F87200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS8 0x4B01F88000 0x4B01F88200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS9 0x4B01F89000 0x4B01F89200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS10 0x4B01F8A000 0x4B01F8A200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX0_CFG_REGS11 0x4B01F8B000 0x4B01F8B200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS0 0x4B01F90000 0x4B01F90200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS1 0x4B01F91000 0x4B01F91200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS2 0x4B01F92000 0x4B01F92200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS3 0x4B01F93000 0x4B01F93200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS4 0x4B01F94000 0x4B01F94200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS5 0x4B01F95000 0x4B01F95200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS6 0x4B01F96000 0x4B01F96200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS7 0x4B01F97000 0x4B01F97200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS8 0x4B01F98000 0x4B01F98200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS9 0x4B01F99000 0x4B01F99200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS10 0x4B01F9A000 0x4B01F9A200 512 B
NAVSS0_VIRT_ALIAS_0_MAILBOX1_CFG_REGS11 0x4B01F9B000 0x4B01F9B200 512 B
NAVSS0_VIRT_ALIAS_0_RINGACC0_CFG_MON 0x4B02000000 0x4B02020000 128 KB
NAVSS0_VIRT_ALIAS_0_TIMERMGR0_CFG_TIMERS 0x4B02200000 0x4B02240000 256 KB
NAVSS0_VIRT_ALIAS_0_TIMERMGR1_CFG_TIMERS 0x4B02240000 0x4B02280000 256 KB
NAVSS0_VIRT_ALIAS_0_SEC_PROXY0_CFG_RT 0x4B02400000 0x4B02600000 2 MB
NAVSS0_VIRT_ALIAS_0_SEC_PROXY0_CFG_SCFG 0x4B02800000 0x4B02A00000 2 MB
NAVSS0_VIRT_ALIAS_0_SEC_PROXY0_SRC_TARGET_DATA 0x4B02C00000 0x4B02E00000 2 MB
NAVSS0_VIRT_ALIAS_0_PROXY0_SRC_TARGET0_DATA 0x4B03000000 0x4B03040000 256 KB
NAVSS0_VIRT_ALIAS_0_PROXY0_CFG_BUF_CFG 0x4B03400000 0x4B03440000 256 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_GCNTRTI 0x4B03800000 0x4B03A00000 2 MB
NAVSS0_VIRT_ALIAS_0_MODSS_INTA0_CFG_INTR 0x4B03C00000 0x4B03C40000 256 KB
NAVSS0_VIRT_ALIAS_0_MODSS_INTA1_CFG_INTR 0x4B03C40000 0x4B03C80000 256 KB
NAVSS0_VIRT_ALIAS_0_UDMASS_INTA0_CFG_INTR 0x4B03D00000 0x4B03E00000 1 MB
NAVSS0_VIRT_ALIAS_0_UDMAP0_CFG_RCHANRT 0x4B04000000 0x4B04080000 512 KB
NAVSS0_VIRT_ALIAS_0_UDMAP0_CFG_TCHANRT 0x4B05000000 0x4B05200000 2 MB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_TCHAN 0x4B05840000 0x4B05841000 4 KB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_RCHAN 0x4B05880000 0x4B05882000 8 KB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_RING 0x4B05900000 0x4B05904000 16 KB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_TCHANRT 0x4B05C00000 0x4B05C10000 64 KB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_RCHANRT 0x4B05D00000 0x4B05D20000 128 KB
NAVSS0_VIRT_ALIAS_0_BCDMA0_CFG_RINGRT 0x4B05E00000 0x4B05E80000 512 KB
NAVSS0_VIRT_ALIAS_0_IO_PVU0_CFG_TLBIF_TLB 0x4B06000000 0x4B06040000 256 KB
NAVSS0_VIRT_ALIAS_0_IO_PVU1_CFG_TLBIF_TLB 0x4B06040000 0x4B06080000 256 KB
NAVSS0_VIRT_ALIAS_0_RINGACC0_SRC_FIFOS 0x4B08000000 0x4B08400000 4 MB
NAVSS0_VIRT_ALIAS_0_RINGACC0_CFG_RT 0x4B0C000000 0x4B0C400000 4 MB
NAVSS0_VIRT_ALIAS_1_MODSS_INTA0_CFG 0x4B10800000 0x4B10800020 32 B
NAVSS0_VIRT_ALIAS_1_MODSS_INTA1_CFG 0x4B10801000 0x4B10801020 32 B
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG 0x4B10802000 0x4B10802020 32 B
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_UNMAP 0x4B10880000 0x4B10890000 64 KB
NAVSS0_VIRT_ALIAS_1_MODSS_INTA0_CFG_IMAP 0x4B10900000 0x4B10902000 8 KB
NAVSS0_VIRT_ALIAS_1_MODSS_INTA1_CFG_IMAP 0x4B10908000 0x4B1090A000 8 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_IMAP 0x4B10940000 0x4B10950000 64 KB
NAVSS0_VIRT_ALIAS_1_NAV_DDR0_VIRTID_CFG_MMRS 0x4B10A02000 0x4B10A02100 256 B
NAVSS0_VIRT_ALIAS_1_NAV_DDR1_VIRTID_CFG_MMRS 0x4B10A03000 0x4B10A03100 256 B
NAVSS0_VIRT_ALIAS_1_UDMAP0_CFG_TCHAN 0x4B10B00000 0x4B10B20000 128 KB
NAVSS0_VIRT_ALIAS_1_UDMAP0_CFG_RCHAN 0x4B10C00000 0x4B10C08000 32 KB
NAVSS0_VIRT_ALIAS_1_UDMAP0_CFG_RFLOW 0x4B10D00000 0x4B10D04000 16 KB
NAVSS0_VIRT_ALIAS_1_SPINLOCK0_CFG 0x4B10E00000 0x4B10E08000 32 KB
NAVSS0_VIRT_ALIAS_1_TIMERMGR0_CFG_CONFIG 0x4B10E80000 0x4B10E80200 512 B
NAVSS0_VIRT_ALIAS_1_TIMERMGR1_CFG_CONFIG 0x4B10E81000 0x4B10E81200 512 B
NAVSS0_VIRT_ALIAS_1_TIMERMGR0_CFG_OES 0x4B10F00000 0x4B10F01000 4 KB
NAVSS0_VIRT_ALIAS_1_TIMERMGR1_CFG_OES 0x4B10F01000 0x4B10F02000 4 KB
NAVSS0_VIRT_ALIAS_1_IO_PVU0_CFG_MMRS 0x4B10F80000 0x4B10F81000 4 KB
NAVSS0_VIRT_ALIAS_1_IO_PVU1_CFG_MMRS 0x4B10F81000 0x4B10F82000 4 KB
NAVSS0_VIRT_ALIAS_1_PVU0_SRC_TOG_CFG 0x4B10F90000 0x4B10F90400 1 KB
NAVSS0_VIRT_ALIAS_1_PVU0_CFG_TOG_CFG 0x4B10F91000 0x4B10F91400 1 KB
NAVSS0_VIRT_ALIAS_1_ECCAGGR0 0x4B11000000 0x4B11000400 1 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_ECCAGGR_CFG 0x4B11001000 0x4B11001400 1 KB
NAVSS0_VIRT_ALIAS_1_VIRTSS_ECCAGGR_CFG 0x4B11002000 0x4B11002400 1 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_GCNTCFG 0x4B11040000 0x4B11044000 16 KB
NAVSS0_VIRT_ALIAS_1_RINGACC0_CFG 0x4B11080000 0x4B110C0000 256 KB
NAVSS0_VIRT_ALIAS_1_REGS0_CFG_MMRS 0x4B110C0000 0x4B110C0100 256 B
NAVSS0_VIRT_ALIAS_1_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B110D0000 0x4B110D0400 1 KB
NAVSS0_VIRT_ALIAS_1_INTR0_CFG_INTR_ROUTER_CFG 0x4B110E0000 0x4B110E4000 16 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_L2G 0x4B11100000 0x4B11102000 8 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_MCAST 0x4B11110000 0x4B11114000 16 KB
NAVSS0_VIRT_ALIAS_1_PROXY0_CFG_BUF_CFG_GCFG 0x4B11120000 0x4B11120100 256 B
NAVSS0_VIRT_ALIAS_1_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B11130000 0x4B11134000 16 KB
NAVSS0_VIRT_ALIAS_1_SEC_PROXY0_CFG_MMRS 0x4B11140000 0x4B11140100 256 B
NAVSS0_VIRT_ALIAS_1_UDMAP0_CFG_GCFG 0x4B11150000 0x4B11150100 256 B
NAVSS0_VIRT_ALIAS_1_RINGACC0_CFG_GCFG 0x4B11160000 0x4B11160400 1 KB
NAVSS0_VIRT_ALIAS_1_PSILSS0_CFG_MMRS 0x4B11170000 0x4B11171000 4 KB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_GCFG 0x4B111A0000 0x4B111A0100 256 B
NAVSS0_VIRT_ALIAS_1_MCRC0_S_CFG_MCRC64 0x4B11F70000 0x4B11F71000 4 KB
NAVSS0_VIRT_ALIAS_1_PSILCFG0_CFG_PROXY 0x4B11F78000 0x4B11F78200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS0 0x4B11F80000 0x4B11F80200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS1 0x4B11F81000 0x4B11F81200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS2 0x4B11F82000 0x4B11F82200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS3 0x4B11F83000 0x4B11F83200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS4 0x4B11F84000 0x4B11F84200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS5 0x4B11F85000 0x4B11F85200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS6 0x4B11F86000 0x4B11F86200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS7 0x4B11F87000 0x4B11F87200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS8 0x4B11F88000 0x4B11F88200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS9 0x4B11F89000 0x4B11F89200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS10 0x4B11F8A000 0x4B11F8A200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX0_CFG_REGS11 0x4B11F8B000 0x4B11F8B200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS0 0x4B11F90000 0x4B11F90200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS1 0x4B11F91000 0x4B11F91200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS2 0x4B11F92000 0x4B11F92200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS3 0x4B11F93000 0x4B11F93200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS4 0x4B11F94000 0x4B11F94200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS5 0x4B11F95000 0x4B11F95200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS6 0x4B11F96000 0x4B11F96200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS7 0x4B11F97000 0x4B11F97200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS8 0x4B11F98000 0x4B11F98200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS9 0x4B11F99000 0x4B11F99200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS10 0x4B11F9A000 0x4B11F9A200 512 B
NAVSS0_VIRT_ALIAS_1_MAILBOX1_CFG_REGS11 0x4B11F9B000 0x4B11F9B200 512 B
NAVSS0_VIRT_ALIAS_1_RINGACC0_CFG_MON 0x4B12000000 0x4B12020000 128 KB
NAVSS0_VIRT_ALIAS_1_TIMERMGR0_CFG_TIMERS 0x4B12200000 0x4B12240000 256 KB
NAVSS0_VIRT_ALIAS_1_TIMERMGR1_CFG_TIMERS 0x4B12240000 0x4B12280000 256 KB
NAVSS0_VIRT_ALIAS_1_SEC_PROXY0_CFG_RT 0x4B12400000 0x4B12600000 2 MB
NAVSS0_VIRT_ALIAS_1_SEC_PROXY0_CFG_SCFG 0x4B12800000 0x4B12A00000 2 MB
NAVSS0_VIRT_ALIAS_1_SEC_PROXY0_SRC_TARGET_DATA 0x4B12C00000 0x4B12E00000 2 MB
NAVSS0_VIRT_ALIAS_1_PROXY0_SRC_TARGET0_DATA 0x4B13000000 0x4B13040000 256 KB
NAVSS0_VIRT_ALIAS_1_PROXY0_CFG_BUF_CFG 0x4B13400000 0x4B13440000 256 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_GCNTRTI 0x4B13800000 0x4B13A00000 2 MB
NAVSS0_VIRT_ALIAS_1_MODSS_INTA0_CFG_INTR 0x4B13C00000 0x4B13C40000 256 KB
NAVSS0_VIRT_ALIAS_1_MODSS_INTA1_CFG_INTR 0x4B13C40000 0x4B13C80000 256 KB
NAVSS0_VIRT_ALIAS_1_UDMASS_INTA0_CFG_INTR 0x4B13D00000 0x4B13E00000 1 MB
NAVSS0_VIRT_ALIAS_1_UDMAP0_CFG_RCHANRT 0x4B14000000 0x4B14080000 512 KB
NAVSS0_VIRT_ALIAS_1_UDMAP0_CFG_TCHANRT 0x4B15000000 0x4B15200000 2 MB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_TCHAN 0x4B15840000 0x4B15841000 4 KB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_RCHAN 0x4B15880000 0x4B15882000 8 KB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_RING 0x4B15900000 0x4B15904000 16 KB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_TCHANRT 0x4B15C00000 0x4B15C10000 64 KB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_RCHANRT 0x4B15D00000 0x4B15D20000 128 KB
NAVSS0_VIRT_ALIAS_1_BCDMA0_CFG_RINGRT 0x4B15E00000 0x4B15E80000 512 KB
NAVSS0_VIRT_ALIAS_1_IO_PVU0_CFG_TLBIF_TLB 0x4B16000000 0x4B16040000 256 KB
NAVSS0_VIRT_ALIAS_1_IO_PVU1_CFG_TLBIF_TLB 0x4B16040000 0x4B16080000 256 KB
NAVSS0_VIRT_ALIAS_1_RINGACC0_SRC_FIFOS 0x4B18000000 0x4B18400000 4 MB
NAVSS0_VIRT_ALIAS_1_RINGACC0_CFG_RT 0x4B1C000000 0x4B1C400000 4 MB
NAVSS0_VIRT_ALIAS_2_MODSS_INTA0_CFG 0x4B20800000 0x4B20800020 32 B
NAVSS0_VIRT_ALIAS_2_MODSS_INTA1_CFG 0x4B20801000 0x4B20801020 32 B
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG 0x4B20802000 0x4B20802020 32 B
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_UNMAP 0x4B20880000 0x4B20890000 64 KB
NAVSS0_VIRT_ALIAS_2_MODSS_INTA0_CFG_IMAP 0x4B20900000 0x4B20902000 8 KB
NAVSS0_VIRT_ALIAS_2_MODSS_INTA1_CFG_IMAP 0x4B20908000 0x4B2090A000 8 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_IMAP 0x4B20940000 0x4B20950000 64 KB
NAVSS0_VIRT_ALIAS_2_NAV_DDR0_VIRTID_CFG_MMRS 0x4B20A02000 0x4B20A02100 256 B
NAVSS0_VIRT_ALIAS_2_NAV_DDR1_VIRTID_CFG_MMRS 0x4B20A03000 0x4B20A03100 256 B
NAVSS0_VIRT_ALIAS_2_UDMAP0_CFG_TCHAN 0x4B20B00000 0x4B20B20000 128 KB
NAVSS0_VIRT_ALIAS_2_UDMAP0_CFG_RCHAN 0x4B20C00000 0x4B20C08000 32 KB
NAVSS0_VIRT_ALIAS_2_UDMAP0_CFG_RFLOW 0x4B20D00000 0x4B20D04000 16 KB
NAVSS0_VIRT_ALIAS_2_SPINLOCK0_CFG 0x4B20E00000 0x4B20E08000 32 KB
NAVSS0_VIRT_ALIAS_2_TIMERMGR0_CFG_CONFIG 0x4B20E80000 0x4B20E80200 512 B
NAVSS0_VIRT_ALIAS_2_TIMERMGR1_CFG_CONFIG 0x4B20E81000 0x4B20E81200 512 B
NAVSS0_VIRT_ALIAS_2_TIMERMGR0_CFG_OES 0x4B20F00000 0x4B20F01000 4 KB
NAVSS0_VIRT_ALIAS_2_TIMERMGR1_CFG_OES 0x4B20F01000 0x4B20F02000 4 KB
NAVSS0_VIRT_ALIAS_2_IO_PVU0_CFG_MMRS 0x4B20F80000 0x4B20F81000 4 KB
NAVSS0_VIRT_ALIAS_2_IO_PVU1_CFG_MMRS 0x4B20F81000 0x4B20F82000 4 KB
NAVSS0_VIRT_ALIAS_2_PVU0_SRC_TOG_CFG 0x4B20F90000 0x4B20F90400 1 KB
NAVSS0_VIRT_ALIAS_2_PVU0_CFG_TOG_CFG 0x4B20F91000 0x4B20F91400 1 KB
NAVSS0_VIRT_ALIAS_2_ECCAGGR0 0x4B21000000 0x4B21000400 1 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_ECCAGGR_CFG 0x4B21001000 0x4B21001400 1 KB
NAVSS0_VIRT_ALIAS_2_VIRTSS_ECCAGGR_CFG 0x4B21002000 0x4B21002400 1 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_GCNTCFG 0x4B21040000 0x4B21044000 16 KB
NAVSS0_VIRT_ALIAS_2_RINGACC0_CFG 0x4B21080000 0x4B210C0000 256 KB
NAVSS0_VIRT_ALIAS_2_REGS0_CFG_MMRS 0x4B210C0000 0x4B210C0100 256 B
NAVSS0_VIRT_ALIAS_2_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B210D0000 0x4B210D0400 1 KB
NAVSS0_VIRT_ALIAS_2_INTR0_CFG_INTR_ROUTER_CFG 0x4B210E0000 0x4B210E4000 16 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_L2G 0x4B21100000 0x4B21102000 8 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_MCAST 0x4B21110000 0x4B21114000 16 KB
NAVSS0_VIRT_ALIAS_2_PROXY0_CFG_BUF_CFG_GCFG 0x4B21120000 0x4B21120100 256 B
NAVSS0_VIRT_ALIAS_2_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B21130000 0x4B21134000 16 KB
NAVSS0_VIRT_ALIAS_2_SEC_PROXY0_CFG_MMRS 0x4B21140000 0x4B21140100 256 B
NAVSS0_VIRT_ALIAS_2_UDMAP0_CFG_GCFG 0x4B21150000 0x4B21150100 256 B
NAVSS0_VIRT_ALIAS_2_RINGACC0_CFG_GCFG 0x4B21160000 0x4B21160400 1 KB
NAVSS0_VIRT_ALIAS_2_PSILSS0_CFG_MMRS 0x4B21170000 0x4B21171000 4 KB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_GCFG 0x4B211A0000 0x4B211A0100 256 B
NAVSS0_VIRT_ALIAS_2_MCRC0_S_CFG_MCRC64 0x4B21F70000 0x4B21F71000 4 KB
NAVSS0_VIRT_ALIAS_2_PSILCFG0_CFG_PROXY 0x4B21F78000 0x4B21F78200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS0 0x4B21F80000 0x4B21F80200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS1 0x4B21F81000 0x4B21F81200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS2 0x4B21F82000 0x4B21F82200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS3 0x4B21F83000 0x4B21F83200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS4 0x4B21F84000 0x4B21F84200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS5 0x4B21F85000 0x4B21F85200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS6 0x4B21F86000 0x4B21F86200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS7 0x4B21F87000 0x4B21F87200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS8 0x4B21F88000 0x4B21F88200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS9 0x4B21F89000 0x4B21F89200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS10 0x4B21F8A000 0x4B21F8A200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX0_CFG_REGS11 0x4B21F8B000 0x4B21F8B200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS0 0x4B21F90000 0x4B21F90200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS1 0x4B21F91000 0x4B21F91200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS2 0x4B21F92000 0x4B21F92200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS3 0x4B21F93000 0x4B21F93200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS4 0x4B21F94000 0x4B21F94200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS5 0x4B21F95000 0x4B21F95200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS6 0x4B21F96000 0x4B21F96200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS7 0x4B21F97000 0x4B21F97200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS8 0x4B21F98000 0x4B21F98200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS9 0x4B21F99000 0x4B21F99200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS10 0x4B21F9A000 0x4B21F9A200 512 B
NAVSS0_VIRT_ALIAS_2_MAILBOX1_CFG_REGS11 0x4B21F9B000 0x4B21F9B200 512 B
NAVSS0_VIRT_ALIAS_2_RINGACC0_CFG_MON 0x4B22000000 0x4B22020000 128 KB
NAVSS0_VIRT_ALIAS_2_TIMERMGR0_CFG_TIMERS 0x4B22200000 0x4B22240000 256 KB
NAVSS0_VIRT_ALIAS_2_TIMERMGR1_CFG_TIMERS 0x4B22240000 0x4B22280000 256 KB
NAVSS0_VIRT_ALIAS_2_SEC_PROXY0_CFG_RT 0x4B22400000 0x4B22600000 2 MB
NAVSS0_VIRT_ALIAS_2_SEC_PROXY0_CFG_SCFG 0x4B22800000 0x4B22A00000 2 MB
NAVSS0_VIRT_ALIAS_2_SEC_PROXY0_SRC_TARGET_DATA 0x4B22C00000 0x4B22E00000 2 MB
NAVSS0_VIRT_ALIAS_2_PROXY0_SRC_TARGET0_DATA 0x4B23000000 0x4B23040000 256 KB
NAVSS0_VIRT_ALIAS_2_PROXY0_CFG_BUF_CFG 0x4B23400000 0x4B23440000 256 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_GCNTRTI 0x4B23800000 0x4B23A00000 2 MB
NAVSS0_VIRT_ALIAS_2_MODSS_INTA0_CFG_INTR 0x4B23C00000 0x4B23C40000 256 KB
NAVSS0_VIRT_ALIAS_2_MODSS_INTA1_CFG_INTR 0x4B23C40000 0x4B23C80000 256 KB
NAVSS0_VIRT_ALIAS_2_UDMASS_INTA0_CFG_INTR 0x4B23D00000 0x4B23E00000 1 MB
NAVSS0_VIRT_ALIAS_2_UDMAP0_CFG_RCHANRT 0x4B24000000 0x4B24080000 512 KB
NAVSS0_VIRT_ALIAS_2_UDMAP0_CFG_TCHANRT 0x4B25000000 0x4B25200000 2 MB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_TCHAN 0x4B25840000 0x4B25841000 4 KB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_RCHAN 0x4B25880000 0x4B25882000 8 KB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_RING 0x4B25900000 0x4B25904000 16 KB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_TCHANRT 0x4B25C00000 0x4B25C10000 64 KB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_RCHANRT 0x4B25D00000 0x4B25D20000 128 KB
NAVSS0_VIRT_ALIAS_2_BCDMA0_CFG_RINGRT 0x4B25E00000 0x4B25E80000 512 KB
NAVSS0_VIRT_ALIAS_2_IO_PVU0_CFG_TLBIF_TLB 0x4B26000000 0x4B26040000 256 KB
NAVSS0_VIRT_ALIAS_2_IO_PVU1_CFG_TLBIF_TLB 0x4B26040000 0x4B26080000 256 KB
NAVSS0_VIRT_ALIAS_2_RINGACC0_SRC_FIFOS 0x4B28000000 0x4B28400000 4 MB
NAVSS0_VIRT_ALIAS_2_RINGACC0_CFG_RT 0x4B2C000000 0x4B2C400000 4 MB
NAVSS0_VIRT_ALIAS_3_MODSS_INTA0_CFG 0x4B30800000 0x4B30800020 32 B
NAVSS0_VIRT_ALIAS_3_MODSS_INTA1_CFG 0x4B30801000 0x4B30801020 32 B
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG 0x4B30802000 0x4B30802020 32 B
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_UNMAP 0x4B30880000 0x4B30890000 64 KB
NAVSS0_VIRT_ALIAS_3_MODSS_INTA0_CFG_IMAP 0x4B30900000 0x4B30902000 8 KB
NAVSS0_VIRT_ALIAS_3_MODSS_INTA1_CFG_IMAP 0x4B30908000 0x4B3090A000 8 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_IMAP 0x4B30940000 0x4B30950000 64 KB
NAVSS0_VIRT_ALIAS_3_NAV_DDR0_VIRTID_CFG_MMRS 0x4B30A02000 0x4B30A02100 256 B
NAVSS0_VIRT_ALIAS_3_NAV_DDR1_VIRTID_CFG_MMRS 0x4B30A03000 0x4B30A03100 256 B
NAVSS0_VIRT_ALIAS_3_UDMAP0_CFG_TCHAN 0x4B30B00000 0x4B30B20000 128 KB
NAVSS0_VIRT_ALIAS_3_UDMAP0_CFG_RCHAN 0x4B30C00000 0x4B30C08000 32 KB
NAVSS0_VIRT_ALIAS_3_UDMAP0_CFG_RFLOW 0x4B30D00000 0x4B30D04000 16 KB
NAVSS0_VIRT_ALIAS_3_SPINLOCK0_CFG 0x4B30E00000 0x4B30E08000 32 KB
NAVSS0_VIRT_ALIAS_3_TIMERMGR0_CFG_CONFIG 0x4B30E80000 0x4B30E80200 512 B
NAVSS0_VIRT_ALIAS_3_TIMERMGR1_CFG_CONFIG 0x4B30E81000 0x4B30E81200 512 B
NAVSS0_VIRT_ALIAS_3_TIMERMGR0_CFG_OES 0x4B30F00000 0x4B30F01000 4 KB
NAVSS0_VIRT_ALIAS_3_TIMERMGR1_CFG_OES 0x4B30F01000 0x4B30F02000 4 KB
NAVSS0_VIRT_ALIAS_3_IO_PVU0_CFG_MMRS 0x4B30F80000 0x4B30F81000 4 KB
NAVSS0_VIRT_ALIAS_3_IO_PVU1_CFG_MMRS 0x4B30F81000 0x4B30F82000 4 KB
NAVSS0_VIRT_ALIAS_3_PVU0_SRC_TOG_CFG 0x4B30F90000 0x4B30F90400 1 KB
NAVSS0_VIRT_ALIAS_3_PVU0_CFG_TOG_CFG 0x4B30F91000 0x4B30F91400 1 KB
NAVSS0_VIRT_ALIAS_3_ECCAGGR0 0x4B31000000 0x4B31000400 1 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_ECCAGGR_CFG 0x4B31001000 0x4B31001400 1 KB
NAVSS0_VIRT_ALIAS_3_VIRTSS_ECCAGGR_CFG 0x4B31002000 0x4B31002400 1 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_GCNTCFG 0x4B31040000 0x4B31044000 16 KB
NAVSS0_VIRT_ALIAS_3_RINGACC0_CFG 0x4B31080000 0x4B310C0000 256 KB
NAVSS0_VIRT_ALIAS_3_REGS0_CFG_MMRS 0x4B310C0000 0x4B310C0100 256 B
NAVSS0_VIRT_ALIAS_3_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B310D0000 0x4B310D0400 1 KB
NAVSS0_VIRT_ALIAS_3_INTR0_CFG_INTR_ROUTER_CFG 0x4B310E0000 0x4B310E4000 16 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_L2G 0x4B31100000 0x4B31102000 8 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_MCAST 0x4B31110000 0x4B31114000 16 KB
NAVSS0_VIRT_ALIAS_3_PROXY0_CFG_BUF_CFG_GCFG 0x4B31120000 0x4B31120100 256 B
NAVSS0_VIRT_ALIAS_3_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B31130000 0x4B31134000 16 KB
NAVSS0_VIRT_ALIAS_3_SEC_PROXY0_CFG_MMRS 0x4B31140000 0x4B31140100 256 B
NAVSS0_VIRT_ALIAS_3_UDMAP0_CFG_GCFG 0x4B31150000 0x4B31150100 256 B
NAVSS0_VIRT_ALIAS_3_RINGACC0_CFG_GCFG 0x4B31160000 0x4B31160400 1 KB
NAVSS0_VIRT_ALIAS_3_PSILSS0_CFG_MMRS 0x4B31170000 0x4B31171000 4 KB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_GCFG 0x4B311A0000 0x4B311A0100 256 B
NAVSS0_VIRT_ALIAS_3_MCRC0_S_CFG_MCRC64 0x4B31F70000 0x4B31F71000 4 KB
NAVSS0_VIRT_ALIAS_3_PSILCFG0_CFG_PROXY 0x4B31F78000 0x4B31F78200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS0 0x4B31F80000 0x4B31F80200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS1 0x4B31F81000 0x4B31F81200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS2 0x4B31F82000 0x4B31F82200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS3 0x4B31F83000 0x4B31F83200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS4 0x4B31F84000 0x4B31F84200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS5 0x4B31F85000 0x4B31F85200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS6 0x4B31F86000 0x4B31F86200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS7 0x4B31F87000 0x4B31F87200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS8 0x4B31F88000 0x4B31F88200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS9 0x4B31F89000 0x4B31F89200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS10 0x4B31F8A000 0x4B31F8A200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX0_CFG_REGS11 0x4B31F8B000 0x4B31F8B200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS0 0x4B31F90000 0x4B31F90200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS1 0x4B31F91000 0x4B31F91200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS2 0x4B31F92000 0x4B31F92200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS3 0x4B31F93000 0x4B31F93200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS4 0x4B31F94000 0x4B31F94200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS5 0x4B31F95000 0x4B31F95200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS6 0x4B31F96000 0x4B31F96200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS7 0x4B31F97000 0x4B31F97200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS8 0x4B31F98000 0x4B31F98200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS9 0x4B31F99000 0x4B31F99200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS10 0x4B31F9A000 0x4B31F9A200 512 B
NAVSS0_VIRT_ALIAS_3_MAILBOX1_CFG_REGS11 0x4B31F9B000 0x4B31F9B200 512 B
NAVSS0_VIRT_ALIAS_3_RINGACC0_CFG_MON 0x4B32000000 0x4B32020000 128 KB
NAVSS0_VIRT_ALIAS_3_TIMERMGR0_CFG_TIMERS 0x4B32200000 0x4B32240000 256 KB
NAVSS0_VIRT_ALIAS_3_TIMERMGR1_CFG_TIMERS 0x4B32240000 0x4B32280000 256 KB
NAVSS0_VIRT_ALIAS_3_SEC_PROXY0_CFG_RT 0x4B32400000 0x4B32600000 2 MB
NAVSS0_VIRT_ALIAS_3_SEC_PROXY0_CFG_SCFG 0x4B32800000 0x4B32A00000 2 MB
NAVSS0_VIRT_ALIAS_3_SEC_PROXY0_SRC_TARGET_DATA 0x4B32C00000 0x4B32E00000 2 MB
NAVSS0_VIRT_ALIAS_3_PROXY0_SRC_TARGET0_DATA 0x4B33000000 0x4B33040000 256 KB
NAVSS0_VIRT_ALIAS_3_PROXY0_CFG_BUF_CFG 0x4B33400000 0x4B33440000 256 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_GCNTRTI 0x4B33800000 0x4B33A00000 2 MB
NAVSS0_VIRT_ALIAS_3_MODSS_INTA0_CFG_INTR 0x4B33C00000 0x4B33C40000 256 KB
NAVSS0_VIRT_ALIAS_3_MODSS_INTA1_CFG_INTR 0x4B33C40000 0x4B33C80000 256 KB
NAVSS0_VIRT_ALIAS_3_UDMASS_INTA0_CFG_INTR 0x4B33D00000 0x4B33E00000 1 MB
NAVSS0_VIRT_ALIAS_3_UDMAP0_CFG_RCHANRT 0x4B34000000 0x4B34080000 512 KB
NAVSS0_VIRT_ALIAS_3_UDMAP0_CFG_TCHANRT 0x4B35000000 0x4B35200000 2 MB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_TCHAN 0x4B35840000 0x4B35841000 4 KB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_RCHAN 0x4B35880000 0x4B35882000 8 KB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_RING 0x4B35900000 0x4B35904000 16 KB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_TCHANRT 0x4B35C00000 0x4B35C10000 64 KB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_RCHANRT 0x4B35D00000 0x4B35D20000 128 KB
NAVSS0_VIRT_ALIAS_3_BCDMA0_CFG_RINGRT 0x4B35E00000 0x4B35E80000 512 KB
NAVSS0_VIRT_ALIAS_3_IO_PVU0_CFG_TLBIF_TLB 0x4B36000000 0x4B36040000 256 KB
NAVSS0_VIRT_ALIAS_3_IO_PVU1_CFG_TLBIF_TLB 0x4B36040000 0x4B36080000 256 KB
NAVSS0_VIRT_ALIAS_3_RINGACC0_SRC_FIFOS 0x4B38000000 0x4B38400000 4 MB
NAVSS0_VIRT_ALIAS_3_RINGACC0_CFG_RT 0x4B3C000000 0x4B3C400000 4 MB
NAVSS0_VIRT_ALIAS_4_MODSS_INTA0_CFG 0x4B40800000 0x4B40800020 32 B
NAVSS0_VIRT_ALIAS_4_MODSS_INTA1_CFG 0x4B40801000 0x4B40801020 32 B
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG 0x4B40802000 0x4B40802020 32 B
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_UNMAP 0x4B40880000 0x4B40890000 64 KB
NAVSS0_VIRT_ALIAS_4_MODSS_INTA0_CFG_IMAP 0x4B40900000 0x4B40902000 8 KB
NAVSS0_VIRT_ALIAS_4_MODSS_INTA1_CFG_IMAP 0x4B40908000 0x4B4090A000 8 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_IMAP 0x4B40940000 0x4B40950000 64 KB
NAVSS0_VIRT_ALIAS_4_NAV_DDR0_VIRTID_CFG_MMRS 0x4B40A02000 0x4B40A02100 256 B
NAVSS0_VIRT_ALIAS_4_NAV_DDR1_VIRTID_CFG_MMRS 0x4B40A03000 0x4B40A03100 256 B
NAVSS0_VIRT_ALIAS_4_UDMAP0_CFG_TCHAN 0x4B40B00000 0x4B40B20000 128 KB
NAVSS0_VIRT_ALIAS_4_UDMAP0_CFG_RCHAN 0x4B40C00000 0x4B40C08000 32 KB
NAVSS0_VIRT_ALIAS_4_UDMAP0_CFG_RFLOW 0x4B40D00000 0x4B40D04000 16 KB
NAVSS0_VIRT_ALIAS_4_SPINLOCK0_CFG 0x4B40E00000 0x4B40E08000 32 KB
NAVSS0_VIRT_ALIAS_4_TIMERMGR0_CFG_CONFIG 0x4B40E80000 0x4B40E80200 512 B
NAVSS0_VIRT_ALIAS_4_TIMERMGR1_CFG_CONFIG 0x4B40E81000 0x4B40E81200 512 B
NAVSS0_VIRT_ALIAS_4_TIMERMGR0_CFG_OES 0x4B40F00000 0x4B40F01000 4 KB
NAVSS0_VIRT_ALIAS_4_TIMERMGR1_CFG_OES 0x4B40F01000 0x4B40F02000 4 KB
NAVSS0_VIRT_ALIAS_4_IO_PVU0_CFG_MMRS 0x4B40F80000 0x4B40F81000 4 KB
NAVSS0_VIRT_ALIAS_4_IO_PVU1_CFG_MMRS 0x4B40F81000 0x4B40F82000 4 KB
NAVSS0_VIRT_ALIAS_4_PVU0_SRC_TOG_CFG 0x4B40F90000 0x4B40F90400 1 KB
NAVSS0_VIRT_ALIAS_4_PVU0_CFG_TOG_CFG 0x4B40F91000 0x4B40F91400 1 KB
NAVSS0_VIRT_ALIAS_4_ECCAGGR0 0x4B41000000 0x4B41000400 1 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_ECCAGGR_CFG 0x4B41001000 0x4B41001400 1 KB
NAVSS0_VIRT_ALIAS_4_VIRTSS_ECCAGGR_CFG 0x4B41002000 0x4B41002400 1 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_GCNTCFG 0x4B41040000 0x4B41044000 16 KB
NAVSS0_VIRT_ALIAS_4_RINGACC0_CFG 0x4B41080000 0x4B410C0000 256 KB
NAVSS0_VIRT_ALIAS_4_REGS0_CFG_MMRS 0x4B410C0000 0x4B410C0100 256 B
NAVSS0_VIRT_ALIAS_4_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B410D0000 0x4B410D0400 1 KB
NAVSS0_VIRT_ALIAS_4_INTR0_CFG_INTR_ROUTER_CFG 0x4B410E0000 0x4B410E4000 16 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_L2G 0x4B41100000 0x4B41102000 8 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_MCAST 0x4B41110000 0x4B41114000 16 KB
NAVSS0_VIRT_ALIAS_4_PROXY0_CFG_BUF_CFG_GCFG 0x4B41120000 0x4B41120100 256 B
NAVSS0_VIRT_ALIAS_4_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B41130000 0x4B41134000 16 KB
NAVSS0_VIRT_ALIAS_4_SEC_PROXY0_CFG_MMRS 0x4B41140000 0x4B41140100 256 B
NAVSS0_VIRT_ALIAS_4_UDMAP0_CFG_GCFG 0x4B41150000 0x4B41150100 256 B
NAVSS0_VIRT_ALIAS_4_RINGACC0_CFG_GCFG 0x4B41160000 0x4B41160400 1 KB
NAVSS0_VIRT_ALIAS_4_PSILSS0_CFG_MMRS 0x4B41170000 0x4B41171000 4 KB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_GCFG 0x4B411A0000 0x4B411A0100 256 B
NAVSS0_VIRT_ALIAS_4_MCRC0_S_CFG_MCRC64 0x4B41F70000 0x4B41F71000 4 KB
NAVSS0_VIRT_ALIAS_4_PSILCFG0_CFG_PROXY 0x4B41F78000 0x4B41F78200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS0 0x4B41F80000 0x4B41F80200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS1 0x4B41F81000 0x4B41F81200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS2 0x4B41F82000 0x4B41F82200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS3 0x4B41F83000 0x4B41F83200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS4 0x4B41F84000 0x4B41F84200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS5 0x4B41F85000 0x4B41F85200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS6 0x4B41F86000 0x4B41F86200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS7 0x4B41F87000 0x4B41F87200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS8 0x4B41F88000 0x4B41F88200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS9 0x4B41F89000 0x4B41F89200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS10 0x4B41F8A000 0x4B41F8A200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX0_CFG_REGS11 0x4B41F8B000 0x4B41F8B200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS0 0x4B41F90000 0x4B41F90200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS1 0x4B41F91000 0x4B41F91200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS2 0x4B41F92000 0x4B41F92200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS3 0x4B41F93000 0x4B41F93200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS4 0x4B41F94000 0x4B41F94200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS5 0x4B41F95000 0x4B41F95200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS6 0x4B41F96000 0x4B41F96200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS7 0x4B41F97000 0x4B41F97200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS8 0x4B41F98000 0x4B41F98200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS9 0x4B41F99000 0x4B41F99200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS10 0x4B41F9A000 0x4B41F9A200 512 B
NAVSS0_VIRT_ALIAS_4_MAILBOX1_CFG_REGS11 0x4B41F9B000 0x4B41F9B200 512 B
NAVSS0_VIRT_ALIAS_4_RINGACC0_CFG_MON 0x4B42000000 0x4B42020000 128 KB
NAVSS0_VIRT_ALIAS_4_TIMERMGR0_CFG_TIMERS 0x4B42200000 0x4B42240000 256 KB
NAVSS0_VIRT_ALIAS_4_TIMERMGR1_CFG_TIMERS 0x4B42240000 0x4B42280000 256 KB
NAVSS0_VIRT_ALIAS_4_SEC_PROXY0_CFG_RT 0x4B42400000 0x4B42600000 2 MB
NAVSS0_VIRT_ALIAS_4_SEC_PROXY0_CFG_SCFG 0x4B42800000 0x4B42A00000 2 MB
NAVSS0_VIRT_ALIAS_4_SEC_PROXY0_SRC_TARGET_DATA 0x4B42C00000 0x4B42E00000 2 MB
NAVSS0_VIRT_ALIAS_4_PROXY0_SRC_TARGET0_DATA 0x4B43000000 0x4B43040000 256 KB
NAVSS0_VIRT_ALIAS_4_PROXY0_CFG_BUF_CFG 0x4B43400000 0x4B43440000 256 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_GCNTRTI 0x4B43800000 0x4B43A00000 2 MB
NAVSS0_VIRT_ALIAS_4_MODSS_INTA0_CFG_INTR 0x4B43C00000 0x4B43C40000 256 KB
NAVSS0_VIRT_ALIAS_4_MODSS_INTA1_CFG_INTR 0x4B43C40000 0x4B43C80000 256 KB
NAVSS0_VIRT_ALIAS_4_UDMASS_INTA0_CFG_INTR 0x4B43D00000 0x4B43E00000 1 MB
NAVSS0_VIRT_ALIAS_4_UDMAP0_CFG_RCHANRT 0x4B44000000 0x4B44080000 512 KB
NAVSS0_VIRT_ALIAS_4_UDMAP0_CFG_TCHANRT 0x4B45000000 0x4B45200000 2 MB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_TCHAN 0x4B45840000 0x4B45841000 4 KB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_RCHAN 0x4B45880000 0x4B45882000 8 KB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_RING 0x4B45900000 0x4B45904000 16 KB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_TCHANRT 0x4B45C00000 0x4B45C10000 64 KB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_RCHANRT 0x4B45D00000 0x4B45D20000 128 KB
NAVSS0_VIRT_ALIAS_4_BCDMA0_CFG_RINGRT 0x4B45E00000 0x4B45E80000 512 KB
NAVSS0_VIRT_ALIAS_4_IO_PVU0_CFG_TLBIF_TLB 0x4B46000000 0x4B46040000 256 KB
NAVSS0_VIRT_ALIAS_4_IO_PVU1_CFG_TLBIF_TLB 0x4B46040000 0x4B46080000 256 KB
NAVSS0_VIRT_ALIAS_4_RINGACC0_SRC_FIFOS 0x4B48000000 0x4B48400000 4 MB
NAVSS0_VIRT_ALIAS_4_RINGACC0_CFG_RT 0x4B4C000000 0x4B4C400000 4 MB
NAVSS0_VIRT_ALIAS_5_MODSS_INTA0_CFG 0x4B50800000 0x4B50800020 32 B
NAVSS0_VIRT_ALIAS_5_MODSS_INTA1_CFG 0x4B50801000 0x4B50801020 32 B
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG 0x4B50802000 0x4B50802020 32 B
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_UNMAP 0x4B50880000 0x4B50890000 64 KB
NAVSS0_VIRT_ALIAS_5_MODSS_INTA0_CFG_IMAP 0x4B50900000 0x4B50902000 8 KB
NAVSS0_VIRT_ALIAS_5_MODSS_INTA1_CFG_IMAP 0x4B50908000 0x4B5090A000 8 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_IMAP 0x4B50940000 0x4B50950000 64 KB
NAVSS0_VIRT_ALIAS_5_NAV_DDR0_VIRTID_CFG_MMRS 0x4B50A02000 0x4B50A02100 256 B
NAVSS0_VIRT_ALIAS_5_NAV_DDR1_VIRTID_CFG_MMRS 0x4B50A03000 0x4B50A03100 256 B
NAVSS0_VIRT_ALIAS_5_UDMAP0_CFG_TCHAN 0x4B50B00000 0x4B50B20000 128 KB
NAVSS0_VIRT_ALIAS_5_UDMAP0_CFG_RCHAN 0x4B50C00000 0x4B50C08000 32 KB
NAVSS0_VIRT_ALIAS_5_UDMAP0_CFG_RFLOW 0x4B50D00000 0x4B50D04000 16 KB
NAVSS0_VIRT_ALIAS_5_SPINLOCK0_CFG 0x4B50E00000 0x4B50E08000 32 KB
NAVSS0_VIRT_ALIAS_5_TIMERMGR0_CFG_CONFIG 0x4B50E80000 0x4B50E80200 512 B
NAVSS0_VIRT_ALIAS_5_TIMERMGR1_CFG_CONFIG 0x4B50E81000 0x4B50E81200 512 B
NAVSS0_VIRT_ALIAS_5_TIMERMGR0_CFG_OES 0x4B50F00000 0x4B50F01000 4 KB
NAVSS0_VIRT_ALIAS_5_TIMERMGR1_CFG_OES 0x4B50F01000 0x4B50F02000 4 KB
NAVSS0_VIRT_ALIAS_5_IO_PVU0_CFG_MMRS 0x4B50F80000 0x4B50F81000 4 KB
NAVSS0_VIRT_ALIAS_5_IO_PVU1_CFG_MMRS 0x4B50F81000 0x4B50F82000 4 KB
NAVSS0_VIRT_ALIAS_5_PVU0_SRC_TOG_CFG 0x4B50F90000 0x4B50F90400 1 KB
NAVSS0_VIRT_ALIAS_5_PVU0_CFG_TOG_CFG 0x4B50F91000 0x4B50F91400 1 KB
NAVSS0_VIRT_ALIAS_5_ECCAGGR0 0x4B51000000 0x4B51000400 1 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_ECCAGGR_CFG 0x4B51001000 0x4B51001400 1 KB
NAVSS0_VIRT_ALIAS_5_VIRTSS_ECCAGGR_CFG 0x4B51002000 0x4B51002400 1 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_GCNTCFG 0x4B51040000 0x4B51044000 16 KB
NAVSS0_VIRT_ALIAS_5_RINGACC0_CFG 0x4B51080000 0x4B510C0000 256 KB
NAVSS0_VIRT_ALIAS_5_REGS0_CFG_MMRS 0x4B510C0000 0x4B510C0100 256 B
NAVSS0_VIRT_ALIAS_5_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B510D0000 0x4B510D0400 1 KB
NAVSS0_VIRT_ALIAS_5_INTR0_CFG_INTR_ROUTER_CFG 0x4B510E0000 0x4B510E4000 16 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_L2G 0x4B51100000 0x4B51102000 8 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_MCAST 0x4B51110000 0x4B51114000 16 KB
NAVSS0_VIRT_ALIAS_5_PROXY0_CFG_BUF_CFG_GCFG 0x4B51120000 0x4B51120100 256 B
NAVSS0_VIRT_ALIAS_5_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B51130000 0x4B51134000 16 KB
NAVSS0_VIRT_ALIAS_5_SEC_PROXY0_CFG_MMRS 0x4B51140000 0x4B51140100 256 B
NAVSS0_VIRT_ALIAS_5_UDMAP0_CFG_GCFG 0x4B51150000 0x4B51150100 256 B
NAVSS0_VIRT_ALIAS_5_RINGACC0_CFG_GCFG 0x4B51160000 0x4B51160400 1 KB
NAVSS0_VIRT_ALIAS_5_PSILSS0_CFG_MMRS 0x4B51170000 0x4B51171000 4 KB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_GCFG 0x4B511A0000 0x4B511A0100 256 B
NAVSS0_VIRT_ALIAS_5_MCRC0_S_CFG_MCRC64 0x4B51F70000 0x4B51F71000 4 KB
NAVSS0_VIRT_ALIAS_5_PSILCFG0_CFG_PROXY 0x4B51F78000 0x4B51F78200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS0 0x4B51F80000 0x4B51F80200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS1 0x4B51F81000 0x4B51F81200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS2 0x4B51F82000 0x4B51F82200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS3 0x4B51F83000 0x4B51F83200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS4 0x4B51F84000 0x4B51F84200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS5 0x4B51F85000 0x4B51F85200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS6 0x4B51F86000 0x4B51F86200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS7 0x4B51F87000 0x4B51F87200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS8 0x4B51F88000 0x4B51F88200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS9 0x4B51F89000 0x4B51F89200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS10 0x4B51F8A000 0x4B51F8A200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX0_CFG_REGS11 0x4B51F8B000 0x4B51F8B200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS0 0x4B51F90000 0x4B51F90200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS1 0x4B51F91000 0x4B51F91200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS2 0x4B51F92000 0x4B51F92200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS3 0x4B51F93000 0x4B51F93200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS4 0x4B51F94000 0x4B51F94200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS5 0x4B51F95000 0x4B51F95200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS6 0x4B51F96000 0x4B51F96200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS7 0x4B51F97000 0x4B51F97200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS8 0x4B51F98000 0x4B51F98200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS9 0x4B51F99000 0x4B51F99200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS10 0x4B51F9A000 0x4B51F9A200 512 B
NAVSS0_VIRT_ALIAS_5_MAILBOX1_CFG_REGS11 0x4B51F9B000 0x4B51F9B200 512 B
NAVSS0_VIRT_ALIAS_5_RINGACC0_CFG_MON 0x4B52000000 0x4B52020000 128 KB
NAVSS0_VIRT_ALIAS_5_TIMERMGR0_CFG_TIMERS 0x4B52200000 0x4B52240000 256 KB
NAVSS0_VIRT_ALIAS_5_TIMERMGR1_CFG_TIMERS 0x4B52240000 0x4B52280000 256 KB
NAVSS0_VIRT_ALIAS_5_SEC_PROXY0_CFG_RT 0x4B52400000 0x4B52600000 2 MB
NAVSS0_VIRT_ALIAS_5_SEC_PROXY0_CFG_SCFG 0x4B52800000 0x4B52A00000 2 MB
NAVSS0_VIRT_ALIAS_5_SEC_PROXY0_SRC_TARGET_DATA 0x4B52C00000 0x4B52E00000 2 MB
NAVSS0_VIRT_ALIAS_5_PROXY0_SRC_TARGET0_DATA 0x4B53000000 0x4B53040000 256 KB
NAVSS0_VIRT_ALIAS_5_PROXY0_CFG_BUF_CFG 0x4B53400000 0x4B53440000 256 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_GCNTRTI 0x4B53800000 0x4B53A00000 2 MB
NAVSS0_VIRT_ALIAS_5_MODSS_INTA0_CFG_INTR 0x4B53C00000 0x4B53C40000 256 KB
NAVSS0_VIRT_ALIAS_5_MODSS_INTA1_CFG_INTR 0x4B53C40000 0x4B53C80000 256 KB
NAVSS0_VIRT_ALIAS_5_UDMASS_INTA0_CFG_INTR 0x4B53D00000 0x4B53E00000 1 MB
NAVSS0_VIRT_ALIAS_5_UDMAP0_CFG_RCHANRT 0x4B54000000 0x4B54080000 512 KB
NAVSS0_VIRT_ALIAS_5_UDMAP0_CFG_TCHANRT 0x4B55000000 0x4B55200000 2 MB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_TCHAN 0x4B55840000 0x4B55841000 4 KB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_RCHAN 0x4B55880000 0x4B55882000 8 KB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_RING 0x4B55900000 0x4B55904000 16 KB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_TCHANRT 0x4B55C00000 0x4B55C10000 64 KB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_RCHANRT 0x4B55D00000 0x4B55D20000 128 KB
NAVSS0_VIRT_ALIAS_5_BCDMA0_CFG_RINGRT 0x4B55E00000 0x4B55E80000 512 KB
NAVSS0_VIRT_ALIAS_5_IO_PVU0_CFG_TLBIF_TLB 0x4B56000000 0x4B56040000 256 KB
NAVSS0_VIRT_ALIAS_5_IO_PVU1_CFG_TLBIF_TLB 0x4B56040000 0x4B56080000 256 KB
NAVSS0_VIRT_ALIAS_5_RINGACC0_SRC_FIFOS 0x4B58000000 0x4B58400000 4 MB
NAVSS0_VIRT_ALIAS_5_RINGACC0_CFG_RT 0x4B5C000000 0x4B5C400000 4 MB
NAVSS0_VIRT_ALIAS_6_MODSS_INTA0_CFG 0x4B60800000 0x4B60800020 32 B
NAVSS0_VIRT_ALIAS_6_MODSS_INTA1_CFG 0x4B60801000 0x4B60801020 32 B
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG 0x4B60802000 0x4B60802020 32 B
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_UNMAP 0x4B60880000 0x4B60890000 64 KB
NAVSS0_VIRT_ALIAS_6_MODSS_INTA0_CFG_IMAP 0x4B60900000 0x4B60902000 8 KB
NAVSS0_VIRT_ALIAS_6_MODSS_INTA1_CFG_IMAP 0x4B60908000 0x4B6090A000 8 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_IMAP 0x4B60940000 0x4B60950000 64 KB
NAVSS0_VIRT_ALIAS_6_NAV_DDR0_VIRTID_CFG_MMRS 0x4B60A02000 0x4B60A02100 256 B
NAVSS0_VIRT_ALIAS_6_NAV_DDR1_VIRTID_CFG_MMRS 0x4B60A03000 0x4B60A03100 256 B
NAVSS0_VIRT_ALIAS_6_UDMAP0_CFG_TCHAN 0x4B60B00000 0x4B60B20000 128 KB
NAVSS0_VIRT_ALIAS_6_UDMAP0_CFG_RCHAN 0x4B60C00000 0x4B60C08000 32 KB
NAVSS0_VIRT_ALIAS_6_UDMAP0_CFG_RFLOW 0x4B60D00000 0x4B60D04000 16 KB
NAVSS0_VIRT_ALIAS_6_SPINLOCK0_CFG 0x4B60E00000 0x4B60E08000 32 KB
NAVSS0_VIRT_ALIAS_6_TIMERMGR0_CFG_CONFIG 0x4B60E80000 0x4B60E80200 512 B
NAVSS0_VIRT_ALIAS_6_TIMERMGR1_CFG_CONFIG 0x4B60E81000 0x4B60E81200 512 B
NAVSS0_VIRT_ALIAS_6_TIMERMGR0_CFG_OES 0x4B60F00000 0x4B60F01000 4 KB
NAVSS0_VIRT_ALIAS_6_TIMERMGR1_CFG_OES 0x4B60F01000 0x4B60F02000 4 KB
NAVSS0_VIRT_ALIAS_6_IO_PVU0_CFG_MMRS 0x4B60F80000 0x4B60F81000 4 KB
NAVSS0_VIRT_ALIAS_6_IO_PVU1_CFG_MMRS 0x4B60F81000 0x4B60F82000 4 KB
NAVSS0_VIRT_ALIAS_6_PVU0_SRC_TOG_CFG 0x4B60F90000 0x4B60F90400 1 KB
NAVSS0_VIRT_ALIAS_6_PVU0_CFG_TOG_CFG 0x4B60F91000 0x4B60F91400 1 KB
NAVSS0_VIRT_ALIAS_6_ECCAGGR0 0x4B61000000 0x4B61000400 1 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_ECCAGGR_CFG 0x4B61001000 0x4B61001400 1 KB
NAVSS0_VIRT_ALIAS_6_VIRTSS_ECCAGGR_CFG 0x4B61002000 0x4B61002400 1 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_GCNTCFG 0x4B61040000 0x4B61044000 16 KB
NAVSS0_VIRT_ALIAS_6_RINGACC0_CFG 0x4B61080000 0x4B610C0000 256 KB
NAVSS0_VIRT_ALIAS_6_REGS0_CFG_MMRS 0x4B610C0000 0x4B610C0100 256 B
NAVSS0_VIRT_ALIAS_6_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B610D0000 0x4B610D0400 1 KB
NAVSS0_VIRT_ALIAS_6_INTR0_CFG_INTR_ROUTER_CFG 0x4B610E0000 0x4B610E4000 16 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_L2G 0x4B61100000 0x4B61102000 8 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_MCAST 0x4B61110000 0x4B61114000 16 KB
NAVSS0_VIRT_ALIAS_6_PROXY0_CFG_BUF_CFG_GCFG 0x4B61120000 0x4B61120100 256 B
NAVSS0_VIRT_ALIAS_6_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B61130000 0x4B61134000 16 KB
NAVSS0_VIRT_ALIAS_6_SEC_PROXY0_CFG_MMRS 0x4B61140000 0x4B61140100 256 B
NAVSS0_VIRT_ALIAS_6_UDMAP0_CFG_GCFG 0x4B61150000 0x4B61150100 256 B
NAVSS0_VIRT_ALIAS_6_RINGACC0_CFG_GCFG 0x4B61160000 0x4B61160400 1 KB
NAVSS0_VIRT_ALIAS_6_PSILSS0_CFG_MMRS 0x4B61170000 0x4B61171000 4 KB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_GCFG 0x4B611A0000 0x4B611A0100 256 B
NAVSS0_VIRT_ALIAS_6_MCRC0_S_CFG_MCRC64 0x4B61F70000 0x4B61F71000 4 KB
NAVSS0_VIRT_ALIAS_6_PSILCFG0_CFG_PROXY 0x4B61F78000 0x4B61F78200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS0 0x4B61F80000 0x4B61F80200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS1 0x4B61F81000 0x4B61F81200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS2 0x4B61F82000 0x4B61F82200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS3 0x4B61F83000 0x4B61F83200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS4 0x4B61F84000 0x4B61F84200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS5 0x4B61F85000 0x4B61F85200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS6 0x4B61F86000 0x4B61F86200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS7 0x4B61F87000 0x4B61F87200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS8 0x4B61F88000 0x4B61F88200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS9 0x4B61F89000 0x4B61F89200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS10 0x4B61F8A000 0x4B61F8A200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX0_CFG_REGS11 0x4B61F8B000 0x4B61F8B200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS0 0x4B61F90000 0x4B61F90200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS1 0x4B61F91000 0x4B61F91200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS2 0x4B61F92000 0x4B61F92200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS3 0x4B61F93000 0x4B61F93200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS4 0x4B61F94000 0x4B61F94200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS5 0x4B61F95000 0x4B61F95200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS6 0x4B61F96000 0x4B61F96200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS7 0x4B61F97000 0x4B61F97200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS8 0x4B61F98000 0x4B61F98200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS9 0x4B61F99000 0x4B61F99200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS10 0x4B61F9A000 0x4B61F9A200 512 B
NAVSS0_VIRT_ALIAS_6_MAILBOX1_CFG_REGS11 0x4B61F9B000 0x4B61F9B200 512 B
NAVSS0_VIRT_ALIAS_6_RINGACC0_CFG_MON 0x4B62000000 0x4B62020000 128 KB
NAVSS0_VIRT_ALIAS_6_TIMERMGR0_CFG_TIMERS 0x4B62200000 0x4B62240000 256 KB
NAVSS0_VIRT_ALIAS_6_TIMERMGR1_CFG_TIMERS 0x4B62240000 0x4B62280000 256 KB
NAVSS0_VIRT_ALIAS_6_SEC_PROXY0_CFG_RT 0x4B62400000 0x4B62600000 2 MB
NAVSS0_VIRT_ALIAS_6_SEC_PROXY0_CFG_SCFG 0x4B62800000 0x4B62A00000 2 MB
NAVSS0_VIRT_ALIAS_6_SEC_PROXY0_SRC_TARGET_DATA 0x4B62C00000 0x4B62E00000 2 MB
NAVSS0_VIRT_ALIAS_6_PROXY0_SRC_TARGET0_DATA 0x4B63000000 0x4B63040000 256 KB
NAVSS0_VIRT_ALIAS_6_PROXY0_CFG_BUF_CFG 0x4B63400000 0x4B63440000 256 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_GCNTRTI 0x4B63800000 0x4B63A00000 2 MB
NAVSS0_VIRT_ALIAS_6_MODSS_INTA0_CFG_INTR 0x4B63C00000 0x4B63C40000 256 KB
NAVSS0_VIRT_ALIAS_6_MODSS_INTA1_CFG_INTR 0x4B63C40000 0x4B63C80000 256 KB
NAVSS0_VIRT_ALIAS_6_UDMASS_INTA0_CFG_INTR 0x4B63D00000 0x4B63E00000 1 MB
NAVSS0_VIRT_ALIAS_6_UDMAP0_CFG_RCHANRT 0x4B64000000 0x4B64080000 512 KB
NAVSS0_VIRT_ALIAS_6_UDMAP0_CFG_TCHANRT 0x4B65000000 0x4B65200000 2 MB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_TCHAN 0x4B65840000 0x4B65841000 4 KB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_RCHAN 0x4B65880000 0x4B65882000 8 KB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_RING 0x4B65900000 0x4B65904000 16 KB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_TCHANRT 0x4B65C00000 0x4B65C10000 64 KB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_RCHANRT 0x4B65D00000 0x4B65D20000 128 KB
NAVSS0_VIRT_ALIAS_6_BCDMA0_CFG_RINGRT 0x4B65E00000 0x4B65E80000 512 KB
NAVSS0_VIRT_ALIAS_6_IO_PVU0_CFG_TLBIF_TLB 0x4B66000000 0x4B66040000 256 KB
NAVSS0_VIRT_ALIAS_6_IO_PVU1_CFG_TLBIF_TLB 0x4B66040000 0x4B66080000 256 KB
NAVSS0_VIRT_ALIAS_6_RINGACC0_SRC_FIFOS 0x4B68000000 0x4B68400000 4 MB
NAVSS0_VIRT_ALIAS_6_RINGACC0_CFG_RT 0x4B6C000000 0x4B6C400000 4 MB
NAVSS0_VIRT_ALIAS_7_MODSS_INTA0_CFG 0x4B70800000 0x4B70800020 32 B
NAVSS0_VIRT_ALIAS_7_MODSS_INTA1_CFG 0x4B70801000 0x4B70801020 32 B
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG 0x4B70802000 0x4B70802020 32 B
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_UNMAP 0x4B70880000 0x4B70890000 64 KB
NAVSS0_VIRT_ALIAS_7_MODSS_INTA0_CFG_IMAP 0x4B70900000 0x4B70902000 8 KB
NAVSS0_VIRT_ALIAS_7_MODSS_INTA1_CFG_IMAP 0x4B70908000 0x4B7090A000 8 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_IMAP 0x4B70940000 0x4B70950000 64 KB
NAVSS0_VIRT_ALIAS_7_NAV_DDR0_VIRTID_CFG_MMRS 0x4B70A02000 0x4B70A02100 256 B
NAVSS0_VIRT_ALIAS_7_NAV_DDR1_VIRTID_CFG_MMRS 0x4B70A03000 0x4B70A03100 256 B
NAVSS0_VIRT_ALIAS_7_UDMAP0_CFG_TCHAN 0x4B70B00000 0x4B70B20000 128 KB
NAVSS0_VIRT_ALIAS_7_UDMAP0_CFG_RCHAN 0x4B70C00000 0x4B70C08000 32 KB
NAVSS0_VIRT_ALIAS_7_UDMAP0_CFG_RFLOW 0x4B70D00000 0x4B70D04000 16 KB
NAVSS0_VIRT_ALIAS_7_SPINLOCK0_CFG 0x4B70E00000 0x4B70E08000 32 KB
NAVSS0_VIRT_ALIAS_7_TIMERMGR0_CFG_CONFIG 0x4B70E80000 0x4B70E80200 512 B
NAVSS0_VIRT_ALIAS_7_TIMERMGR1_CFG_CONFIG 0x4B70E81000 0x4B70E81200 512 B
NAVSS0_VIRT_ALIAS_7_TIMERMGR0_CFG_OES 0x4B70F00000 0x4B70F01000 4 KB
NAVSS0_VIRT_ALIAS_7_TIMERMGR1_CFG_OES 0x4B70F01000 0x4B70F02000 4 KB
NAVSS0_VIRT_ALIAS_7_IO_PVU0_CFG_MMRS 0x4B70F80000 0x4B70F81000 4 KB
NAVSS0_VIRT_ALIAS_7_IO_PVU1_CFG_MMRS 0x4B70F81000 0x4B70F82000 4 KB
NAVSS0_VIRT_ALIAS_7_PVU0_SRC_TOG_CFG 0x4B70F90000 0x4B70F90400 1 KB
NAVSS0_VIRT_ALIAS_7_PVU0_CFG_TOG_CFG 0x4B70F91000 0x4B70F91400 1 KB
NAVSS0_VIRT_ALIAS_7_ECCAGGR0 0x4B71000000 0x4B71000400 1 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_ECCAGGR_CFG 0x4B71001000 0x4B71001400 1 KB
NAVSS0_VIRT_ALIAS_7_VIRTSS_ECCAGGR_CFG 0x4B71002000 0x4B71002400 1 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_GCNTCFG 0x4B71040000 0x4B71044000 16 KB
NAVSS0_VIRT_ALIAS_7_RINGACC0_CFG 0x4B71080000 0x4B710C0000 256 KB
NAVSS0_VIRT_ALIAS_7_REGS0_CFG_MMRS 0x4B710C0000 0x4B710C0100 256 B
NAVSS0_VIRT_ALIAS_7_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B710D0000 0x4B710D0400 1 KB
NAVSS0_VIRT_ALIAS_7_INTR0_CFG_INTR_ROUTER_CFG 0x4B710E0000 0x4B710E4000 16 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_L2G 0x4B71100000 0x4B71102000 8 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_MCAST 0x4B71110000 0x4B71114000 16 KB
NAVSS0_VIRT_ALIAS_7_PROXY0_CFG_BUF_CFG_GCFG 0x4B71120000 0x4B71120100 256 B
NAVSS0_VIRT_ALIAS_7_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B71130000 0x4B71134000 16 KB
NAVSS0_VIRT_ALIAS_7_SEC_PROXY0_CFG_MMRS 0x4B71140000 0x4B71140100 256 B
NAVSS0_VIRT_ALIAS_7_UDMAP0_CFG_GCFG 0x4B71150000 0x4B71150100 256 B
NAVSS0_VIRT_ALIAS_7_RINGACC0_CFG_GCFG 0x4B71160000 0x4B71160400 1 KB
NAVSS0_VIRT_ALIAS_7_PSILSS0_CFG_MMRS 0x4B71170000 0x4B71171000 4 KB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_GCFG 0x4B711A0000 0x4B711A0100 256 B
NAVSS0_VIRT_ALIAS_7_MCRC0_S_CFG_MCRC64 0x4B71F70000 0x4B71F71000 4 KB
NAVSS0_VIRT_ALIAS_7_PSILCFG0_CFG_PROXY 0x4B71F78000 0x4B71F78200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS0 0x4B71F80000 0x4B71F80200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS1 0x4B71F81000 0x4B71F81200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS2 0x4B71F82000 0x4B71F82200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS3 0x4B71F83000 0x4B71F83200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS4 0x4B71F84000 0x4B71F84200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS5 0x4B71F85000 0x4B71F85200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS6 0x4B71F86000 0x4B71F86200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS7 0x4B71F87000 0x4B71F87200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS8 0x4B71F88000 0x4B71F88200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS9 0x4B71F89000 0x4B71F89200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS10 0x4B71F8A000 0x4B71F8A200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX0_CFG_REGS11 0x4B71F8B000 0x4B71F8B200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS0 0x4B71F90000 0x4B71F90200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS1 0x4B71F91000 0x4B71F91200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS2 0x4B71F92000 0x4B71F92200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS3 0x4B71F93000 0x4B71F93200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS4 0x4B71F94000 0x4B71F94200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS5 0x4B71F95000 0x4B71F95200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS6 0x4B71F96000 0x4B71F96200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS7 0x4B71F97000 0x4B71F97200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS8 0x4B71F98000 0x4B71F98200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS9 0x4B71F99000 0x4B71F99200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS10 0x4B71F9A000 0x4B71F9A200 512 B
NAVSS0_VIRT_ALIAS_7_MAILBOX1_CFG_REGS11 0x4B71F9B000 0x4B71F9B200 512 B
NAVSS0_VIRT_ALIAS_7_RINGACC0_CFG_MON 0x4B72000000 0x4B72020000 128 KB
NAVSS0_VIRT_ALIAS_7_TIMERMGR0_CFG_TIMERS 0x4B72200000 0x4B72240000 256 KB
NAVSS0_VIRT_ALIAS_7_TIMERMGR1_CFG_TIMERS 0x4B72240000 0x4B72280000 256 KB
NAVSS0_VIRT_ALIAS_7_SEC_PROXY0_CFG_RT 0x4B72400000 0x4B72600000 2 MB
NAVSS0_VIRT_ALIAS_7_SEC_PROXY0_CFG_SCFG 0x4B72800000 0x4B72A00000 2 MB
NAVSS0_VIRT_ALIAS_7_SEC_PROXY0_SRC_TARGET_DATA 0x4B72C00000 0x4B72E00000 2 MB
NAVSS0_VIRT_ALIAS_7_PROXY0_SRC_TARGET0_DATA 0x4B73000000 0x4B73040000 256 KB
NAVSS0_VIRT_ALIAS_7_PROXY0_CFG_BUF_CFG 0x4B73400000 0x4B73440000 256 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_GCNTRTI 0x4B73800000 0x4B73A00000 2 MB
NAVSS0_VIRT_ALIAS_7_MODSS_INTA0_CFG_INTR 0x4B73C00000 0x4B73C40000 256 KB
NAVSS0_VIRT_ALIAS_7_MODSS_INTA1_CFG_INTR 0x4B73C40000 0x4B73C80000 256 KB
NAVSS0_VIRT_ALIAS_7_UDMASS_INTA0_CFG_INTR 0x4B73D00000 0x4B73E00000 1 MB
NAVSS0_VIRT_ALIAS_7_UDMAP0_CFG_RCHANRT 0x4B74000000 0x4B74080000 512 KB
NAVSS0_VIRT_ALIAS_7_UDMAP0_CFG_TCHANRT 0x4B75000000 0x4B75200000 2 MB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_TCHAN 0x4B75840000 0x4B75841000 4 KB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_RCHAN 0x4B75880000 0x4B75882000 8 KB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_RING 0x4B75900000 0x4B75904000 16 KB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_TCHANRT 0x4B75C00000 0x4B75C10000 64 KB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_RCHANRT 0x4B75D00000 0x4B75D20000 128 KB
NAVSS0_VIRT_ALIAS_7_BCDMA0_CFG_RINGRT 0x4B75E00000 0x4B75E80000 512 KB
NAVSS0_VIRT_ALIAS_7_IO_PVU0_CFG_TLBIF_TLB 0x4B76000000 0x4B76040000 256 KB
NAVSS0_VIRT_ALIAS_7_IO_PVU1_CFG_TLBIF_TLB 0x4B76040000 0x4B76080000 256 KB
NAVSS0_VIRT_ALIAS_7_RINGACC0_SRC_FIFOS 0x4B78000000 0x4B78400000 4 MB
NAVSS0_VIRT_ALIAS_7_RINGACC0_CFG_RT 0x4B7C000000 0x4B7C400000 4 MB
NAVSS0_VIRT_ALIAS_8_MODSS_INTA0_CFG 0x4B80800000 0x4B80800020 32 B
NAVSS0_VIRT_ALIAS_8_MODSS_INTA1_CFG 0x4B80801000 0x4B80801020 32 B
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG 0x4B80802000 0x4B80802020 32 B
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_UNMAP 0x4B80880000 0x4B80890000 64 KB
NAVSS0_VIRT_ALIAS_8_MODSS_INTA0_CFG_IMAP 0x4B80900000 0x4B80902000 8 KB
NAVSS0_VIRT_ALIAS_8_MODSS_INTA1_CFG_IMAP 0x4B80908000 0x4B8090A000 8 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_IMAP 0x4B80940000 0x4B80950000 64 KB
NAVSS0_VIRT_ALIAS_8_NAV_DDR0_VIRTID_CFG_MMRS 0x4B80A02000 0x4B80A02100 256 B
NAVSS0_VIRT_ALIAS_8_NAV_DDR1_VIRTID_CFG_MMRS 0x4B80A03000 0x4B80A03100 256 B
NAVSS0_VIRT_ALIAS_8_UDMAP0_CFG_TCHAN 0x4B80B00000 0x4B80B20000 128 KB
NAVSS0_VIRT_ALIAS_8_UDMAP0_CFG_RCHAN 0x4B80C00000 0x4B80C08000 32 KB
NAVSS0_VIRT_ALIAS_8_UDMAP0_CFG_RFLOW 0x4B80D00000 0x4B80D04000 16 KB
NAVSS0_VIRT_ALIAS_8_SPINLOCK0_CFG 0x4B80E00000 0x4B80E08000 32 KB
NAVSS0_VIRT_ALIAS_8_TIMERMGR0_CFG_CONFIG 0x4B80E80000 0x4B80E80200 512 B
NAVSS0_VIRT_ALIAS_8_TIMERMGR1_CFG_CONFIG 0x4B80E81000 0x4B80E81200 512 B
NAVSS0_VIRT_ALIAS_8_TIMERMGR0_CFG_OES 0x4B80F00000 0x4B80F01000 4 KB
NAVSS0_VIRT_ALIAS_8_TIMERMGR1_CFG_OES 0x4B80F01000 0x4B80F02000 4 KB
NAVSS0_VIRT_ALIAS_8_IO_PVU0_CFG_MMRS 0x4B80F80000 0x4B80F81000 4 KB
NAVSS0_VIRT_ALIAS_8_IO_PVU1_CFG_MMRS 0x4B80F81000 0x4B80F82000 4 KB
NAVSS0_VIRT_ALIAS_8_PVU0_SRC_TOG_CFG 0x4B80F90000 0x4B80F90400 1 KB
NAVSS0_VIRT_ALIAS_8_PVU0_CFG_TOG_CFG 0x4B80F91000 0x4B80F91400 1 KB
NAVSS0_VIRT_ALIAS_8_ECCAGGR0 0x4B81000000 0x4B81000400 1 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_ECCAGGR_CFG 0x4B81001000 0x4B81001400 1 KB
NAVSS0_VIRT_ALIAS_8_VIRTSS_ECCAGGR_CFG 0x4B81002000 0x4B81002400 1 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_GCNTCFG 0x4B81040000 0x4B81044000 16 KB
NAVSS0_VIRT_ALIAS_8_RINGACC0_CFG 0x4B81080000 0x4B810C0000 256 KB
NAVSS0_VIRT_ALIAS_8_REGS0_CFG_MMRS 0x4B810C0000 0x4B810C0100 256 B
NAVSS0_VIRT_ALIAS_8_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B810D0000 0x4B810D0400 1 KB
NAVSS0_VIRT_ALIAS_8_INTR0_CFG_INTR_ROUTER_CFG 0x4B810E0000 0x4B810E4000 16 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_L2G 0x4B81100000 0x4B81102000 8 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_MCAST 0x4B81110000 0x4B81114000 16 KB
NAVSS0_VIRT_ALIAS_8_PROXY0_CFG_BUF_CFG_GCFG 0x4B81120000 0x4B81120100 256 B
NAVSS0_VIRT_ALIAS_8_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B81130000 0x4B81134000 16 KB
NAVSS0_VIRT_ALIAS_8_SEC_PROXY0_CFG_MMRS 0x4B81140000 0x4B81140100 256 B
NAVSS0_VIRT_ALIAS_8_UDMAP0_CFG_GCFG 0x4B81150000 0x4B81150100 256 B
NAVSS0_VIRT_ALIAS_8_RINGACC0_CFG_GCFG 0x4B81160000 0x4B81160400 1 KB
NAVSS0_VIRT_ALIAS_8_PSILSS0_CFG_MMRS 0x4B81170000 0x4B81171000 4 KB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_GCFG 0x4B811A0000 0x4B811A0100 256 B
NAVSS0_VIRT_ALIAS_8_MCRC0_S_CFG_MCRC64 0x4B81F70000 0x4B81F71000 4 KB
NAVSS0_VIRT_ALIAS_8_PSILCFG0_CFG_PROXY 0x4B81F78000 0x4B81F78200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS0 0x4B81F80000 0x4B81F80200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS1 0x4B81F81000 0x4B81F81200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS2 0x4B81F82000 0x4B81F82200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS3 0x4B81F83000 0x4B81F83200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS4 0x4B81F84000 0x4B81F84200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS5 0x4B81F85000 0x4B81F85200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS6 0x4B81F86000 0x4B81F86200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS7 0x4B81F87000 0x4B81F87200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS8 0x4B81F88000 0x4B81F88200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS9 0x4B81F89000 0x4B81F89200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS10 0x4B81F8A000 0x4B81F8A200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX0_CFG_REGS11 0x4B81F8B000 0x4B81F8B200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS0 0x4B81F90000 0x4B81F90200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS1 0x4B81F91000 0x4B81F91200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS2 0x4B81F92000 0x4B81F92200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS3 0x4B81F93000 0x4B81F93200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS4 0x4B81F94000 0x4B81F94200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS5 0x4B81F95000 0x4B81F95200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS6 0x4B81F96000 0x4B81F96200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS7 0x4B81F97000 0x4B81F97200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS8 0x4B81F98000 0x4B81F98200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS9 0x4B81F99000 0x4B81F99200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS10 0x4B81F9A000 0x4B81F9A200 512 B
NAVSS0_VIRT_ALIAS_8_MAILBOX1_CFG_REGS11 0x4B81F9B000 0x4B81F9B200 512 B
NAVSS0_VIRT_ALIAS_8_RINGACC0_CFG_MON 0x4B82000000 0x4B82020000 128 KB
NAVSS0_VIRT_ALIAS_8_TIMERMGR0_CFG_TIMERS 0x4B82200000 0x4B82240000 256 KB
NAVSS0_VIRT_ALIAS_8_TIMERMGR1_CFG_TIMERS 0x4B82240000 0x4B82280000 256 KB
NAVSS0_VIRT_ALIAS_8_SEC_PROXY0_CFG_RT 0x4B82400000 0x4B82600000 2 MB
NAVSS0_VIRT_ALIAS_8_SEC_PROXY0_CFG_SCFG 0x4B82800000 0x4B82A00000 2 MB
NAVSS0_VIRT_ALIAS_8_SEC_PROXY0_SRC_TARGET_DATA 0x4B82C00000 0x4B82E00000 2 MB
NAVSS0_VIRT_ALIAS_8_PROXY0_SRC_TARGET0_DATA 0x4B83000000 0x4B83040000 256 KB
NAVSS0_VIRT_ALIAS_8_PROXY0_CFG_BUF_CFG 0x4B83400000 0x4B83440000 256 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_GCNTRTI 0x4B83800000 0x4B83A00000 2 MB
NAVSS0_VIRT_ALIAS_8_MODSS_INTA0_CFG_INTR 0x4B83C00000 0x4B83C40000 256 KB
NAVSS0_VIRT_ALIAS_8_MODSS_INTA1_CFG_INTR 0x4B83C40000 0x4B83C80000 256 KB
NAVSS0_VIRT_ALIAS_8_UDMASS_INTA0_CFG_INTR 0x4B83D00000 0x4B83E00000 1 MB
NAVSS0_VIRT_ALIAS_8_UDMAP0_CFG_RCHANRT 0x4B84000000 0x4B84080000 512 KB
NAVSS0_VIRT_ALIAS_8_UDMAP0_CFG_TCHANRT 0x4B85000000 0x4B85200000 2 MB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_TCHAN 0x4B85840000 0x4B85841000 4 KB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_RCHAN 0x4B85880000 0x4B85882000 8 KB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_RING 0x4B85900000 0x4B85904000 16 KB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_TCHANRT 0x4B85C00000 0x4B85C10000 64 KB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_RCHANRT 0x4B85D00000 0x4B85D20000 128 KB
NAVSS0_VIRT_ALIAS_8_BCDMA0_CFG_RINGRT 0x4B85E00000 0x4B85E80000 512 KB
NAVSS0_VIRT_ALIAS_8_IO_PVU0_CFG_TLBIF_TLB 0x4B86000000 0x4B86040000 256 KB
NAVSS0_VIRT_ALIAS_8_IO_PVU1_CFG_TLBIF_TLB 0x4B86040000 0x4B86080000 256 KB
NAVSS0_VIRT_ALIAS_8_RINGACC0_SRC_FIFOS 0x4B88000000 0x4B88400000 4 MB
NAVSS0_VIRT_ALIAS_8_RINGACC0_CFG_RT 0x4B8C000000 0x4B8C400000 4 MB
NAVSS0_VIRT_ALIAS_9_MODSS_INTA0_CFG 0x4B90800000 0x4B90800020 32 B
NAVSS0_VIRT_ALIAS_9_MODSS_INTA1_CFG 0x4B90801000 0x4B90801020 32 B
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG 0x4B90802000 0x4B90802020 32 B
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_UNMAP 0x4B90880000 0x4B90890000 64 KB
NAVSS0_VIRT_ALIAS_9_MODSS_INTA0_CFG_IMAP 0x4B90900000 0x4B90902000 8 KB
NAVSS0_VIRT_ALIAS_9_MODSS_INTA1_CFG_IMAP 0x4B90908000 0x4B9090A000 8 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_IMAP 0x4B90940000 0x4B90950000 64 KB
NAVSS0_VIRT_ALIAS_9_NAV_DDR0_VIRTID_CFG_MMRS 0x4B90A02000 0x4B90A02100 256 B
NAVSS0_VIRT_ALIAS_9_NAV_DDR1_VIRTID_CFG_MMRS 0x4B90A03000 0x4B90A03100 256 B
NAVSS0_VIRT_ALIAS_9_UDMAP0_CFG_TCHAN 0x4B90B00000 0x4B90B20000 128 KB
NAVSS0_VIRT_ALIAS_9_UDMAP0_CFG_RCHAN 0x4B90C00000 0x4B90C08000 32 KB
NAVSS0_VIRT_ALIAS_9_UDMAP0_CFG_RFLOW 0x4B90D00000 0x4B90D04000 16 KB
NAVSS0_VIRT_ALIAS_9_SPINLOCK0_CFG 0x4B90E00000 0x4B90E08000 32 KB
NAVSS0_VIRT_ALIAS_9_TIMERMGR0_CFG_CONFIG 0x4B90E80000 0x4B90E80200 512 B
NAVSS0_VIRT_ALIAS_9_TIMERMGR1_CFG_CONFIG 0x4B90E81000 0x4B90E81200 512 B
NAVSS0_VIRT_ALIAS_9_TIMERMGR0_CFG_OES 0x4B90F00000 0x4B90F01000 4 KB
NAVSS0_VIRT_ALIAS_9_TIMERMGR1_CFG_OES 0x4B90F01000 0x4B90F02000 4 KB
NAVSS0_VIRT_ALIAS_9_IO_PVU0_CFG_MMRS 0x4B90F80000 0x4B90F81000 4 KB
NAVSS0_VIRT_ALIAS_9_IO_PVU1_CFG_MMRS 0x4B90F81000 0x4B90F82000 4 KB
NAVSS0_VIRT_ALIAS_9_PVU0_SRC_TOG_CFG 0x4B90F90000 0x4B90F90400 1 KB
NAVSS0_VIRT_ALIAS_9_PVU0_CFG_TOG_CFG 0x4B90F91000 0x4B90F91400 1 KB
NAVSS0_VIRT_ALIAS_9_ECCAGGR0 0x4B91000000 0x4B91000400 1 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_ECCAGGR_CFG 0x4B91001000 0x4B91001400 1 KB
NAVSS0_VIRT_ALIAS_9_VIRTSS_ECCAGGR_CFG 0x4B91002000 0x4B91002400 1 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_GCNTCFG 0x4B91040000 0x4B91044000 16 KB
NAVSS0_VIRT_ALIAS_9_RINGACC0_CFG 0x4B91080000 0x4B910C0000 256 KB
NAVSS0_VIRT_ALIAS_9_REGS0_CFG_MMRS 0x4B910C0000 0x4B910C0100 256 B
NAVSS0_VIRT_ALIAS_9_CPTS0_S_VBUSP_CPTS_VBUSP 0x4B910D0000 0x4B910D0400 1 KB
NAVSS0_VIRT_ALIAS_9_INTR0_CFG_INTR_ROUTER_CFG 0x4B910E0000 0x4B910E4000 16 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_L2G 0x4B91100000 0x4B91102000 8 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_MCAST 0x4B91110000 0x4B91114000 16 KB
NAVSS0_VIRT_ALIAS_9_PROXY0_CFG_BUF_CFG_GCFG 0x4B91120000 0x4B91120100 256 B
NAVSS0_VIRT_ALIAS_9_PROXY0_CFG_BUFRAM_SLV_RAM 0x4B91130000 0x4B91134000 16 KB
NAVSS0_VIRT_ALIAS_9_SEC_PROXY0_CFG_MMRS 0x4B91140000 0x4B91140100 256 B
NAVSS0_VIRT_ALIAS_9_UDMAP0_CFG_GCFG 0x4B91150000 0x4B91150100 256 B
NAVSS0_VIRT_ALIAS_9_RINGACC0_CFG_GCFG 0x4B91160000 0x4B91160400 1 KB
NAVSS0_VIRT_ALIAS_9_PSILSS0_CFG_MMRS 0x4B91170000 0x4B91171000 4 KB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_GCFG 0x4B911A0000 0x4B911A0100 256 B
NAVSS0_VIRT_ALIAS_9_MCRC0_S_CFG_MCRC64 0x4B91F70000 0x4B91F71000 4 KB
NAVSS0_VIRT_ALIAS_9_PSILCFG0_CFG_PROXY 0x4B91F78000 0x4B91F78200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS0 0x4B91F80000 0x4B91F80200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS1 0x4B91F81000 0x4B91F81200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS2 0x4B91F82000 0x4B91F82200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS3 0x4B91F83000 0x4B91F83200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS4 0x4B91F84000 0x4B91F84200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS5 0x4B91F85000 0x4B91F85200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS6 0x4B91F86000 0x4B91F86200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS7 0x4B91F87000 0x4B91F87200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS8 0x4B91F88000 0x4B91F88200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS9 0x4B91F89000 0x4B91F89200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS10 0x4B91F8A000 0x4B91F8A200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX0_CFG_REGS11 0x4B91F8B000 0x4B91F8B200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS0 0x4B91F90000 0x4B91F90200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS1 0x4B91F91000 0x4B91F91200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS2 0x4B91F92000 0x4B91F92200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS3 0x4B91F93000 0x4B91F93200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS4 0x4B91F94000 0x4B91F94200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS5 0x4B91F95000 0x4B91F95200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS6 0x4B91F96000 0x4B91F96200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS7 0x4B91F97000 0x4B91F97200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS8 0x4B91F98000 0x4B91F98200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS9 0x4B91F99000 0x4B91F99200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS10 0x4B91F9A000 0x4B91F9A200 512 B
NAVSS0_VIRT_ALIAS_9_MAILBOX1_CFG_REGS11 0x4B91F9B000 0x4B91F9B200 512 B
NAVSS0_VIRT_ALIAS_9_RINGACC0_CFG_MON 0x4B92000000 0x4B92020000 128 KB
NAVSS0_VIRT_ALIAS_9_TIMERMGR0_CFG_TIMERS 0x4B92200000 0x4B92240000 256 KB
NAVSS0_VIRT_ALIAS_9_TIMERMGR1_CFG_TIMERS 0x4B92240000 0x4B92280000 256 KB
NAVSS0_VIRT_ALIAS_9_SEC_PROXY0_CFG_RT 0x4B92400000 0x4B92600000 2 MB
NAVSS0_VIRT_ALIAS_9_SEC_PROXY0_CFG_SCFG 0x4B92800000 0x4B92A00000 2 MB
NAVSS0_VIRT_ALIAS_9_SEC_PROXY0_SRC_TARGET_DATA 0x4B92C00000 0x4B92E00000 2 MB
NAVSS0_VIRT_ALIAS_9_PROXY0_SRC_TARGET0_DATA 0x4B93000000 0x4B93040000 256 KB
NAVSS0_VIRT_ALIAS_9_PROXY0_CFG_BUF_CFG 0x4B93400000 0x4B93440000 256 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_GCNTRTI 0x4B93800000 0x4B93A00000 2 MB
NAVSS0_VIRT_ALIAS_9_MODSS_INTA0_CFG_INTR 0x4B93C00000 0x4B93C40000 256 KB
NAVSS0_VIRT_ALIAS_9_MODSS_INTA1_CFG_INTR 0x4B93C40000 0x4B93C80000 256 KB
NAVSS0_VIRT_ALIAS_9_UDMASS_INTA0_CFG_INTR 0x4B93D00000 0x4B93E00000 1 MB
NAVSS0_VIRT_ALIAS_9_UDMAP0_CFG_RCHANRT 0x4B94000000 0x4B94080000 512 KB
NAVSS0_VIRT_ALIAS_9_UDMAP0_CFG_TCHANRT 0x4B95000000 0x4B95200000 2 MB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_TCHAN 0x4B95840000 0x4B95841000 4 KB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_RCHAN 0x4B95880000 0x4B95882000 8 KB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_RING 0x4B95900000 0x4B95904000 16 KB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_TCHANRT 0x4B95C00000 0x4B95C10000 64 KB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_RCHANRT 0x4B95D00000 0x4B95D20000 128 KB
NAVSS0_VIRT_ALIAS_9_BCDMA0_CFG_RINGRT 0x4B95E00000 0x4B95E80000 512 KB
NAVSS0_VIRT_ALIAS_9_IO_PVU0_CFG_TLBIF_TLB 0x4B96000000 0x4B96040000 256 KB
NAVSS0_VIRT_ALIAS_9_IO_PVU1_CFG_TLBIF_TLB 0x4B96040000 0x4B96080000 256 KB
NAVSS0_VIRT_ALIAS_9_RINGACC0_SRC_FIFOS 0x4B98000000 0x4B98400000 4 MB
NAVSS0_VIRT_ALIAS_9_RINGACC0_CFG_RT 0x4B9C000000 0x4B9C400000 4 MB
NAVSS0_VIRT_ALIAS_10_MODSS_INTA0_CFG 0x4BA0800000 0x4BA0800020 32 B
NAVSS0_VIRT_ALIAS_10_MODSS_INTA1_CFG 0x4BA0801000 0x4BA0801020 32 B
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG 0x4BA0802000 0x4BA0802020 32 B
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_UNMAP 0x4BA0880000 0x4BA0890000 64 KB
NAVSS0_VIRT_ALIAS_10_MODSS_INTA0_CFG_IMAP 0x4BA0900000 0x4BA0902000 8 KB
NAVSS0_VIRT_ALIAS_10_MODSS_INTA1_CFG_IMAP 0x4BA0908000 0x4BA090A000 8 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_IMAP 0x4BA0940000 0x4BA0950000 64 KB
NAVSS0_VIRT_ALIAS_10_NAV_DDR0_VIRTID_CFG_MMRS 0x4BA0A02000 0x4BA0A02100 256 B
NAVSS0_VIRT_ALIAS_10_NAV_DDR1_VIRTID_CFG_MMRS 0x4BA0A03000 0x4BA0A03100 256 B
NAVSS0_VIRT_ALIAS_10_UDMAP0_CFG_TCHAN 0x4BA0B00000 0x4BA0B20000 128 KB
NAVSS0_VIRT_ALIAS_10_UDMAP0_CFG_RCHAN 0x4BA0C00000 0x4BA0C08000 32 KB
NAVSS0_VIRT_ALIAS_10_UDMAP0_CFG_RFLOW 0x4BA0D00000 0x4BA0D04000 16 KB
NAVSS0_VIRT_ALIAS_10_SPINLOCK0_CFG 0x4BA0E00000 0x4BA0E08000 32 KB
NAVSS0_VIRT_ALIAS_10_TIMERMGR0_CFG_CONFIG 0x4BA0E80000 0x4BA0E80200 512 B
NAVSS0_VIRT_ALIAS_10_TIMERMGR1_CFG_CONFIG 0x4BA0E81000 0x4BA0E81200 512 B
NAVSS0_VIRT_ALIAS_10_TIMERMGR0_CFG_OES 0x4BA0F00000 0x4BA0F01000 4 KB
NAVSS0_VIRT_ALIAS_10_TIMERMGR1_CFG_OES 0x4BA0F01000 0x4BA0F02000 4 KB
NAVSS0_VIRT_ALIAS_10_IO_PVU0_CFG_MMRS 0x4BA0F80000 0x4BA0F81000 4 KB
NAVSS0_VIRT_ALIAS_10_IO_PVU1_CFG_MMRS 0x4BA0F81000 0x4BA0F82000 4 KB
NAVSS0_VIRT_ALIAS_10_PVU0_SRC_TOG_CFG 0x4BA0F90000 0x4BA0F90400 1 KB
NAVSS0_VIRT_ALIAS_10_PVU0_CFG_TOG_CFG 0x4BA0F91000 0x4BA0F91400 1 KB
NAVSS0_VIRT_ALIAS_10_ECCAGGR0 0x4BA1000000 0x4BA1000400 1 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_ECCAGGR_CFG 0x4BA1001000 0x4BA1001400 1 KB
NAVSS0_VIRT_ALIAS_10_VIRTSS_ECCAGGR_CFG 0x4BA1002000 0x4BA1002400 1 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_GCNTCFG 0x4BA1040000 0x4BA1044000 16 KB
NAVSS0_VIRT_ALIAS_10_RINGACC0_CFG 0x4BA1080000 0x4BA10C0000 256 KB
NAVSS0_VIRT_ALIAS_10_REGS0_CFG_MMRS 0x4BA10C0000 0x4BA10C0100 256 B
NAVSS0_VIRT_ALIAS_10_CPTS0_S_VBUSP_CPTS_VBUSP 0x4BA10D0000 0x4BA10D0400 1 KB
NAVSS0_VIRT_ALIAS_10_INTR0_CFG_INTR_ROUTER_CFG 0x4BA10E0000 0x4BA10E4000 16 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_L2G 0x4BA1100000 0x4BA1102000 8 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_MCAST 0x4BA1110000 0x4BA1114000 16 KB
NAVSS0_VIRT_ALIAS_10_PROXY0_CFG_BUF_CFG_GCFG 0x4BA1120000 0x4BA1120100 256 B
NAVSS0_VIRT_ALIAS_10_PROXY0_CFG_BUFRAM_SLV_RAM 0x4BA1130000 0x4BA1134000 16 KB
NAVSS0_VIRT_ALIAS_10_SEC_PROXY0_CFG_MMRS 0x4BA1140000 0x4BA1140100 256 B
NAVSS0_VIRT_ALIAS_10_UDMAP0_CFG_GCFG 0x4BA1150000 0x4BA1150100 256 B
NAVSS0_VIRT_ALIAS_10_RINGACC0_CFG_GCFG 0x4BA1160000 0x4BA1160400 1 KB
NAVSS0_VIRT_ALIAS_10_PSILSS0_CFG_MMRS 0x4BA1170000 0x4BA1171000 4 KB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_GCFG 0x4BA11A0000 0x4BA11A0100 256 B
NAVSS0_VIRT_ALIAS_10_MCRC0_S_CFG_MCRC64 0x4BA1F70000 0x4BA1F71000 4 KB
NAVSS0_VIRT_ALIAS_10_PSILCFG0_CFG_PROXY 0x4BA1F78000 0x4BA1F78200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS0 0x4BA1F80000 0x4BA1F80200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS1 0x4BA1F81000 0x4BA1F81200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS2 0x4BA1F82000 0x4BA1F82200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS3 0x4BA1F83000 0x4BA1F83200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS4 0x4BA1F84000 0x4BA1F84200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS5 0x4BA1F85000 0x4BA1F85200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS6 0x4BA1F86000 0x4BA1F86200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS7 0x4BA1F87000 0x4BA1F87200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS8 0x4BA1F88000 0x4BA1F88200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS9 0x4BA1F89000 0x4BA1F89200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS10 0x4BA1F8A000 0x4BA1F8A200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX0_CFG_REGS11 0x4BA1F8B000 0x4BA1F8B200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS0 0x4BA1F90000 0x4BA1F90200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS1 0x4BA1F91000 0x4BA1F91200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS2 0x4BA1F92000 0x4BA1F92200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS3 0x4BA1F93000 0x4BA1F93200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS4 0x4BA1F94000 0x4BA1F94200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS5 0x4BA1F95000 0x4BA1F95200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS6 0x4BA1F96000 0x4BA1F96200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS7 0x4BA1F97000 0x4BA1F97200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS8 0x4BA1F98000 0x4BA1F98200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS9 0x4BA1F99000 0x4BA1F99200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS10 0x4BA1F9A000 0x4BA1F9A200 512 B
NAVSS0_VIRT_ALIAS_10_MAILBOX1_CFG_REGS11 0x4BA1F9B000 0x4BA1F9B200 512 B
NAVSS0_VIRT_ALIAS_10_RINGACC0_CFG_MON 0x4BA2000000 0x4BA2020000 128 KB
NAVSS0_VIRT_ALIAS_10_TIMERMGR0_CFG_TIMERS 0x4BA2200000 0x4BA2240000 256 KB
NAVSS0_VIRT_ALIAS_10_TIMERMGR1_CFG_TIMERS 0x4BA2240000 0x4BA2280000 256 KB
NAVSS0_VIRT_ALIAS_10_SEC_PROXY0_CFG_RT 0x4BA2400000 0x4BA2600000 2 MB
NAVSS0_VIRT_ALIAS_10_SEC_PROXY0_CFG_SCFG 0x4BA2800000 0x4BA2A00000 2 MB
NAVSS0_VIRT_ALIAS_10_SEC_PROXY0_SRC_TARGET_DATA 0x4BA2C00000 0x4BA2E00000 2 MB
NAVSS0_VIRT_ALIAS_10_PROXY0_SRC_TARGET0_DATA 0x4BA3000000 0x4BA3040000 256 KB
NAVSS0_VIRT_ALIAS_10_PROXY0_CFG_BUF_CFG 0x4BA3400000 0x4BA3440000 256 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_GCNTRTI 0x4BA3800000 0x4BA3A00000 2 MB
NAVSS0_VIRT_ALIAS_10_MODSS_INTA0_CFG_INTR 0x4BA3C00000 0x4BA3C40000 256 KB
NAVSS0_VIRT_ALIAS_10_MODSS_INTA1_CFG_INTR 0x4BA3C40000 0x4BA3C80000 256 KB
NAVSS0_VIRT_ALIAS_10_UDMASS_INTA0_CFG_INTR 0x4BA3D00000 0x4BA3E00000 1 MB
NAVSS0_VIRT_ALIAS_10_UDMAP0_CFG_RCHANRT 0x4BA4000000 0x4BA4080000 512 KB
NAVSS0_VIRT_ALIAS_10_UDMAP0_CFG_TCHANRT 0x4BA5000000 0x4BA5200000 2 MB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_TCHAN 0x4BA5840000 0x4BA5841000 4 KB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_RCHAN 0x4BA5880000 0x4BA5882000 8 KB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_RING 0x4BA5900000 0x4BA5904000 16 KB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_TCHANRT 0x4BA5C00000 0x4BA5C10000 64 KB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_RCHANRT 0x4BA5D00000 0x4BA5D20000 128 KB
NAVSS0_VIRT_ALIAS_10_BCDMA0_CFG_RINGRT 0x4BA5E00000 0x4BA5E80000 512 KB
NAVSS0_VIRT_ALIAS_10_IO_PVU0_CFG_TLBIF_TLB 0x4BA6000000 0x4BA6040000 256 KB
NAVSS0_VIRT_ALIAS_10_IO_PVU1_CFG_TLBIF_TLB 0x4BA6040000 0x4BA6080000 256 KB
NAVSS0_VIRT_ALIAS_10_RINGACC0_SRC_FIFOS 0x4BA8000000 0x4BA8400000 4 MB
NAVSS0_VIRT_ALIAS_10_RINGACC0_CFG_RT 0x4BAC000000 0x4BAC400000 4 MB
NAVSS0_VIRT_ALIAS_11_MODSS_INTA0_CFG 0x4BB0800000 0x4BB0800020 32 B
NAVSS0_VIRT_ALIAS_11_MODSS_INTA1_CFG 0x4BB0801000 0x4BB0801020 32 B
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG 0x4BB0802000 0x4BB0802020 32 B
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_UNMAP 0x4BB0880000 0x4BB0890000 64 KB
NAVSS0_VIRT_ALIAS_11_MODSS_INTA0_CFG_IMAP 0x4BB0900000 0x4BB0902000 8 KB
NAVSS0_VIRT_ALIAS_11_MODSS_INTA1_CFG_IMAP 0x4BB0908000 0x4BB090A000 8 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_IMAP 0x4BB0940000 0x4BB0950000 64 KB
NAVSS0_VIRT_ALIAS_11_NAV_DDR0_VIRTID_CFG_MMRS 0x4BB0A02000 0x4BB0A02100 256 B
NAVSS0_VIRT_ALIAS_11_NAV_DDR1_VIRTID_CFG_MMRS 0x4BB0A03000 0x4BB0A03100 256 B
NAVSS0_VIRT_ALIAS_11_UDMAP0_CFG_TCHAN 0x4BB0B00000 0x4BB0B20000 128 KB
NAVSS0_VIRT_ALIAS_11_UDMAP0_CFG_RCHAN 0x4BB0C00000 0x4BB0C08000 32 KB
NAVSS0_VIRT_ALIAS_11_UDMAP0_CFG_RFLOW 0x4BB0D00000 0x4BB0D04000 16 KB
NAVSS0_VIRT_ALIAS_11_SPINLOCK0_CFG 0x4BB0E00000 0x4BB0E08000 32 KB
NAVSS0_VIRT_ALIAS_11_TIMERMGR0_CFG_CONFIG 0x4BB0E80000 0x4BB0E80200 512 B
NAVSS0_VIRT_ALIAS_11_TIMERMGR1_CFG_CONFIG 0x4BB0E81000 0x4BB0E81200 512 B
NAVSS0_VIRT_ALIAS_11_TIMERMGR0_CFG_OES 0x4BB0F00000 0x4BB0F01000 4 KB
NAVSS0_VIRT_ALIAS_11_TIMERMGR1_CFG_OES 0x4BB0F01000 0x4BB0F02000 4 KB
NAVSS0_VIRT_ALIAS_11_IO_PVU0_CFG_MMRS 0x4BB0F80000 0x4BB0F81000 4 KB
NAVSS0_VIRT_ALIAS_11_IO_PVU1_CFG_MMRS 0x4BB0F81000 0x4BB0F82000 4 KB
NAVSS0_VIRT_ALIAS_11_PVU0_SRC_TOG_CFG 0x4BB0F90000 0x4BB0F90400 1 KB
NAVSS0_VIRT_ALIAS_11_PVU0_CFG_TOG_CFG 0x4BB0F91000 0x4BB0F91400 1 KB
NAVSS0_VIRT_ALIAS_11_ECCAGGR0 0x4BB1000000 0x4BB1000400 1 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_ECCAGGR_CFG 0x4BB1001000 0x4BB1001400 1 KB
NAVSS0_VIRT_ALIAS_11_VIRTSS_ECCAGGR_CFG 0x4BB1002000 0x4BB1002400 1 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_GCNTCFG 0x4BB1040000 0x4BB1044000 16 KB
NAVSS0_VIRT_ALIAS_11_RINGACC0_CFG 0x4BB1080000 0x4BB10C0000 256 KB
NAVSS0_VIRT_ALIAS_11_REGS0_CFG_MMRS 0x4BB10C0000 0x4BB10C0100 256 B
NAVSS0_VIRT_ALIAS_11_CPTS0_S_VBUSP_CPTS_VBUSP 0x4BB10D0000 0x4BB10D0400 1 KB
NAVSS0_VIRT_ALIAS_11_INTR0_CFG_INTR_ROUTER_CFG 0x4BB10E0000 0x4BB10E4000 16 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_L2G 0x4BB1100000 0x4BB1102000 8 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_MCAST 0x4BB1110000 0x4BB1114000 16 KB
NAVSS0_VIRT_ALIAS_11_PROXY0_CFG_BUF_CFG_GCFG 0x4BB1120000 0x4BB1120100 256 B
NAVSS0_VIRT_ALIAS_11_PROXY0_CFG_BUFRAM_SLV_RAM 0x4BB1130000 0x4BB1134000 16 KB
NAVSS0_VIRT_ALIAS_11_SEC_PROXY0_CFG_MMRS 0x4BB1140000 0x4BB1140100 256 B
NAVSS0_VIRT_ALIAS_11_UDMAP0_CFG_GCFG 0x4BB1150000 0x4BB1150100 256 B
NAVSS0_VIRT_ALIAS_11_RINGACC0_CFG_GCFG 0x4BB1160000 0x4BB1160400 1 KB
NAVSS0_VIRT_ALIAS_11_PSILSS0_CFG_MMRS 0x4BB1170000 0x4BB1171000 4 KB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_GCFG 0x4BB11A0000 0x4BB11A0100 256 B
NAVSS0_VIRT_ALIAS_11_MCRC0_S_CFG_MCRC64 0x4BB1F70000 0x4BB1F71000 4 KB
NAVSS0_VIRT_ALIAS_11_PSILCFG0_CFG_PROXY 0x4BB1F78000 0x4BB1F78200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS0 0x4BB1F80000 0x4BB1F80200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS1 0x4BB1F81000 0x4BB1F81200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS2 0x4BB1F82000 0x4BB1F82200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS3 0x4BB1F83000 0x4BB1F83200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS4 0x4BB1F84000 0x4BB1F84200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS5 0x4BB1F85000 0x4BB1F85200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS6 0x4BB1F86000 0x4BB1F86200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS7 0x4BB1F87000 0x4BB1F87200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS8 0x4BB1F88000 0x4BB1F88200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS9 0x4BB1F89000 0x4BB1F89200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS10 0x4BB1F8A000 0x4BB1F8A200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX0_CFG_REGS11 0x4BB1F8B000 0x4BB1F8B200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS0 0x4BB1F90000 0x4BB1F90200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS1 0x4BB1F91000 0x4BB1F91200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS2 0x4BB1F92000 0x4BB1F92200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS3 0x4BB1F93000 0x4BB1F93200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS4 0x4BB1F94000 0x4BB1F94200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS5 0x4BB1F95000 0x4BB1F95200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS6 0x4BB1F96000 0x4BB1F96200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS7 0x4BB1F97000 0x4BB1F97200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS8 0x4BB1F98000 0x4BB1F98200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS9 0x4BB1F99000 0x4BB1F99200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS10 0x4BB1F9A000 0x4BB1F9A200 512 B
NAVSS0_VIRT_ALIAS_11_MAILBOX1_CFG_REGS11 0x4BB1F9B000 0x4BB1F9B200 512 B
NAVSS0_VIRT_ALIAS_11_RINGACC0_CFG_MON 0x4BB2000000 0x4BB2020000 128 KB
NAVSS0_VIRT_ALIAS_11_TIMERMGR0_CFG_TIMERS 0x4BB2200000 0x4BB2240000 256 KB
NAVSS0_VIRT_ALIAS_11_TIMERMGR1_CFG_TIMERS 0x4BB2240000 0x4BB2280000 256 KB
NAVSS0_VIRT_ALIAS_11_SEC_PROXY0_CFG_RT 0x4BB2400000 0x4BB2600000 2 MB
NAVSS0_VIRT_ALIAS_11_SEC_PROXY0_CFG_SCFG 0x4BB2800000 0x4BB2A00000 2 MB
NAVSS0_VIRT_ALIAS_11_SEC_PROXY0_SRC_TARGET_DATA 0x4BB2C00000 0x4BB2E00000 2 MB
NAVSS0_VIRT_ALIAS_11_PROXY0_SRC_TARGET0_DATA 0x4BB3000000 0x4BB3040000 256 KB
NAVSS0_VIRT_ALIAS_11_PROXY0_CFG_BUF_CFG 0x4BB3400000 0x4BB3440000 256 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_GCNTRTI 0x4BB3800000 0x4BB3A00000 2 MB
NAVSS0_VIRT_ALIAS_11_MODSS_INTA0_CFG_INTR 0x4BB3C00000 0x4BB3C40000 256 KB
NAVSS0_VIRT_ALIAS_11_MODSS_INTA1_CFG_INTR 0x4BB3C40000 0x4BB3C80000 256 KB
NAVSS0_VIRT_ALIAS_11_UDMASS_INTA0_CFG_INTR 0x4BB3D00000 0x4BB3E00000 1 MB
NAVSS0_VIRT_ALIAS_11_UDMAP0_CFG_RCHANRT 0x4BB4000000 0x4BB4080000 512 KB
NAVSS0_VIRT_ALIAS_11_UDMAP0_CFG_TCHANRT 0x4BB5000000 0x4BB5200000 2 MB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_TCHAN 0x4BB5840000 0x4BB5841000 4 KB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_RCHAN 0x4BB5880000 0x4BB5882000 8 KB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_RING 0x4BB5900000 0x4BB5904000 16 KB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_TCHANRT 0x4BB5C00000 0x4BB5C10000 64 KB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_RCHANRT 0x4BB5D00000 0x4BB5D20000 128 KB
NAVSS0_VIRT_ALIAS_11_BCDMA0_CFG_RINGRT 0x4BB5E00000 0x4BB5E80000 512 KB
NAVSS0_VIRT_ALIAS_11_IO_PVU0_CFG_TLBIF_TLB 0x4BB6000000 0x4BB6040000 256 KB
NAVSS0_VIRT_ALIAS_11_IO_PVU1_CFG_TLBIF_TLB 0x4BB6040000 0x4BB6080000 256 KB
NAVSS0_VIRT_ALIAS_11_RINGACC0_SRC_FIFOS 0x4BB8000000 0x4BB8400000 4 MB
NAVSS0_VIRT_ALIAS_11_RINGACC0_CFG_RT 0x4BBC000000 0x4BBC400000 4 MB
NAVSS0_VIRT_ALIAS_12_MODSS_INTA0_CFG 0x4BC0800000 0x4BC0800020 32 B
NAVSS0_VIRT_ALIAS_12_MODSS_INTA1_CFG 0x4BC0801000 0x4BC0801020 32 B
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG 0x4BC0802000 0x4BC0802020 32 B
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_UNMAP 0x4BC0880000 0x4BC0890000 64 KB
NAVSS0_VIRT_ALIAS_12_MODSS_INTA0_CFG_IMAP 0x4BC0900000 0x4BC0902000 8 KB
NAVSS0_VIRT_ALIAS_12_MODSS_INTA1_CFG_IMAP 0x4BC0908000 0x4BC090A000 8 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_IMAP 0x4BC0940000 0x4BC0950000 64 KB
NAVSS0_VIRT_ALIAS_12_NAV_DDR0_VIRTID_CFG_MMRS 0x4BC0A02000 0x4BC0A02100 256 B
NAVSS0_VIRT_ALIAS_12_NAV_DDR1_VIRTID_CFG_MMRS 0x4BC0A03000 0x4BC0A03100 256 B
NAVSS0_VIRT_ALIAS_12_UDMAP0_CFG_TCHAN 0x4BC0B00000 0x4BC0B20000 128 KB
NAVSS0_VIRT_ALIAS_12_UDMAP0_CFG_RCHAN 0x4BC0C00000 0x4BC0C08000 32 KB
NAVSS0_VIRT_ALIAS_12_UDMAP0_CFG_RFLOW 0x4BC0D00000 0x4BC0D04000 16 KB
NAVSS0_VIRT_ALIAS_12_SPINLOCK0_CFG 0x4BC0E00000 0x4BC0E08000 32 KB
NAVSS0_VIRT_ALIAS_12_TIMERMGR0_CFG_CONFIG 0x4BC0E80000 0x4BC0E80200 512 B
NAVSS0_VIRT_ALIAS_12_TIMERMGR1_CFG_CONFIG 0x4BC0E81000 0x4BC0E81200 512 B
NAVSS0_VIRT_ALIAS_12_TIMERMGR0_CFG_OES 0x4BC0F00000 0x4BC0F01000 4 KB
NAVSS0_VIRT_ALIAS_12_TIMERMGR1_CFG_OES 0x4BC0F01000 0x4BC0F02000 4 KB
NAVSS0_VIRT_ALIAS_12_IO_PVU0_CFG_MMRS 0x4BC0F80000 0x4BC0F81000 4 KB
NAVSS0_VIRT_ALIAS_12_IO_PVU1_CFG_MMRS 0x4BC0F81000 0x4BC0F82000 4 KB
NAVSS0_VIRT_ALIAS_12_PVU0_SRC_TOG_CFG 0x4BC0F90000 0x4BC0F90400 1 KB
NAVSS0_VIRT_ALIAS_12_PVU0_CFG_TOG_CFG 0x4BC0F91000 0x4BC0F91400 1 KB
NAVSS0_VIRT_ALIAS_12_ECCAGGR0 0x4BC1000000 0x4BC1000400 1 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_ECCAGGR_CFG 0x4BC1001000 0x4BC1001400 1 KB
NAVSS0_VIRT_ALIAS_12_VIRTSS_ECCAGGR_CFG 0x4BC1002000 0x4BC1002400 1 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_GCNTCFG 0x4BC1040000 0x4BC1044000 16 KB
NAVSS0_VIRT_ALIAS_12_RINGACC0_CFG 0x4BC1080000 0x4BC10C0000 256 KB
NAVSS0_VIRT_ALIAS_12_REGS0_CFG_MMRS 0x4BC10C0000 0x4BC10C0100 256 B
NAVSS0_VIRT_ALIAS_12_CPTS0_S_VBUSP_CPTS_VBUSP 0x4BC10D0000 0x4BC10D0400 1 KB
NAVSS0_VIRT_ALIAS_12_INTR0_CFG_INTR_ROUTER_CFG 0x4BC10E0000 0x4BC10E4000 16 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_L2G 0x4BC1100000 0x4BC1102000 8 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_MCAST 0x4BC1110000 0x4BC1114000 16 KB
NAVSS0_VIRT_ALIAS_12_PROXY0_CFG_BUF_CFG_GCFG 0x4BC1120000 0x4BC1120100 256 B
NAVSS0_VIRT_ALIAS_12_PROXY0_CFG_BUFRAM_SLV_RAM 0x4BC1130000 0x4BC1134000 16 KB
NAVSS0_VIRT_ALIAS_12_SEC_PROXY0_CFG_MMRS 0x4BC1140000 0x4BC1140100 256 B
NAVSS0_VIRT_ALIAS_12_UDMAP0_CFG_GCFG 0x4BC1150000 0x4BC1150100 256 B
NAVSS0_VIRT_ALIAS_12_RINGACC0_CFG_GCFG 0x4BC1160000 0x4BC1160400 1 KB
NAVSS0_VIRT_ALIAS_12_PSILSS0_CFG_MMRS 0x4BC1170000 0x4BC1171000 4 KB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_GCFG 0x4BC11A0000 0x4BC11A0100 256 B
NAVSS0_VIRT_ALIAS_12_MCRC0_S_CFG_MCRC64 0x4BC1F70000 0x4BC1F71000 4 KB
NAVSS0_VIRT_ALIAS_12_PSILCFG0_CFG_PROXY 0x4BC1F78000 0x4BC1F78200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS0 0x4BC1F80000 0x4BC1F80200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS1 0x4BC1F81000 0x4BC1F81200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS2 0x4BC1F82000 0x4BC1F82200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS3 0x4BC1F83000 0x4BC1F83200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS4 0x4BC1F84000 0x4BC1F84200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS5 0x4BC1F85000 0x4BC1F85200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS6 0x4BC1F86000 0x4BC1F86200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS7 0x4BC1F87000 0x4BC1F87200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS8 0x4BC1F88000 0x4BC1F88200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS9 0x4BC1F89000 0x4BC1F89200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS10 0x4BC1F8A000 0x4BC1F8A200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX0_CFG_REGS11 0x4BC1F8B000 0x4BC1F8B200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS0 0x4BC1F90000 0x4BC1F90200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS1 0x4BC1F91000 0x4BC1F91200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS2 0x4BC1F92000 0x4BC1F92200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS3 0x4BC1F93000 0x4BC1F93200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS4 0x4BC1F94000 0x4BC1F94200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS5 0x4BC1F95000 0x4BC1F95200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS6 0x4BC1F96000 0x4BC1F96200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS7 0x4BC1F97000 0x4BC1F97200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS8 0x4BC1F98000 0x4BC1F98200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS9 0x4BC1F99000 0x4BC1F99200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS10 0x4BC1F9A000 0x4BC1F9A200 512 B
NAVSS0_VIRT_ALIAS_12_MAILBOX1_CFG_REGS11 0x4BC1F9B000 0x4BC1F9B200 512 B
NAVSS0_VIRT_ALIAS_12_RINGACC0_CFG_MON 0x4BC2000000 0x4BC2020000 128 KB
NAVSS0_VIRT_ALIAS_12_TIMERMGR0_CFG_TIMERS 0x4BC2200000 0x4BC2240000 256 KB
NAVSS0_VIRT_ALIAS_12_TIMERMGR1_CFG_TIMERS 0x4BC2240000 0x4BC2280000 256 KB
NAVSS0_VIRT_ALIAS_12_SEC_PROXY0_CFG_RT 0x4BC2400000 0x4BC2600000 2 MB
NAVSS0_VIRT_ALIAS_12_SEC_PROXY0_CFG_SCFG 0x4BC2800000 0x4BC2A00000 2 MB
NAVSS0_VIRT_ALIAS_12_SEC_PROXY0_SRC_TARGET_DATA 0x4BC2C00000 0x4BC2E00000 2 MB
NAVSS0_VIRT_ALIAS_12_PROXY0_SRC_TARGET0_DATA 0x4BC3000000 0x4BC3040000 256 KB
NAVSS0_VIRT_ALIAS_12_PROXY0_CFG_BUF_CFG 0x4BC3400000 0x4BC3440000 256 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_GCNTRTI 0x4BC3800000 0x4BC3A00000 2 MB
NAVSS0_VIRT_ALIAS_12_MODSS_INTA0_CFG_INTR 0x4BC3C00000 0x4BC3C40000 256 KB
NAVSS0_VIRT_ALIAS_12_MODSS_INTA1_CFG_INTR 0x4BC3C40000 0x4BC3C80000 256 KB
NAVSS0_VIRT_ALIAS_12_UDMASS_INTA0_CFG_INTR 0x4BC3D00000 0x4BC3E00000 1 MB
NAVSS0_VIRT_ALIAS_12_UDMAP0_CFG_RCHANRT 0x4BC4000000 0x4BC4080000 512 KB
NAVSS0_VIRT_ALIAS_12_UDMAP0_CFG_TCHANRT 0x4BC5000000 0x4BC5200000 2 MB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_TCHAN 0x4BC5840000 0x4BC5841000 4 KB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_RCHAN 0x4BC5880000 0x4BC5882000 8 KB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_RING 0x4BC5900000 0x4BC5904000 16 KB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_TCHANRT 0x4BC5C00000 0x4BC5C10000 64 KB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_RCHANRT 0x4BC5D00000 0x4BC5D20000 128 KB
NAVSS0_VIRT_ALIAS_12_BCDMA0_CFG_RINGRT 0x4BC5E00000 0x4BC5E80000 512 KB
NAVSS0_VIRT_ALIAS_12_IO_PVU0_CFG_TLBIF_TLB 0x4BC6000000 0x4BC6040000 256 KB
NAVSS0_VIRT_ALIAS_12_IO_PVU1_CFG_TLBIF_TLB 0x4BC6040000 0x4BC6080000 256 KB
NAVSS0_VIRT_ALIAS_12_RINGACC0_SRC_FIFOS 0x4BC8000000 0x4BC8400000 4 MB
NAVSS0_VIRT_ALIAS_12_RINGACC0_CFG_RT 0x4BCC000000 0x4BCC400000 4 MB
NAVSS0_VIRT_ALIAS_13_MODSS_INTA0_CFG 0x4BD0800000 0x4BD0800020 32 B
NAVSS0_VIRT_ALIAS_13_MODSS_INTA1_CFG 0x4BD0801000 0x4BD0801020 32 B
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG 0x4BD0802000 0x4BD0802020 32 B
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_UNMAP 0x4BD0880000 0x4BD0890000 64 KB
NAVSS0_VIRT_ALIAS_13_MODSS_INTA0_CFG_IMAP 0x4BD0900000 0x4BD0902000 8 KB
NAVSS0_VIRT_ALIAS_13_MODSS_INTA1_CFG_IMAP 0x4BD0908000 0x4BD090A000 8 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_IMAP 0x4BD0940000 0x4BD0950000 64 KB
NAVSS0_VIRT_ALIAS_13_NAV_DDR0_VIRTID_CFG_MMRS 0x4BD0A02000 0x4BD0A02100 256 B
NAVSS0_VIRT_ALIAS_13_NAV_DDR1_VIRTID_CFG_MMRS 0x4BD0A03000 0x4BD0A03100 256 B
NAVSS0_VIRT_ALIAS_13_UDMAP0_CFG_TCHAN 0x4BD0B00000 0x4BD0B20000 128 KB
NAVSS0_VIRT_ALIAS_13_UDMAP0_CFG_RCHAN 0x4BD0C00000 0x4BD0C08000 32 KB
NAVSS0_VIRT_ALIAS_13_UDMAP0_CFG_RFLOW 0x4BD0D00000 0x4BD0D04000 16 KB
NAVSS0_VIRT_ALIAS_13_SPINLOCK0_CFG 0x4BD0E00000 0x4BD0E08000 32 KB
NAVSS0_VIRT_ALIAS_13_TIMERMGR0_CFG_CONFIG 0x4BD0E80000 0x4BD0E80200 512 B
NAVSS0_VIRT_ALIAS_13_TIMERMGR1_CFG_CONFIG 0x4BD0E81000 0x4BD0E81200 512 B
NAVSS0_VIRT_ALIAS_13_TIMERMGR0_CFG_OES 0x4BD0F00000 0x4BD0F01000 4 KB
NAVSS0_VIRT_ALIAS_13_TIMERMGR1_CFG_OES 0x4BD0F01000 0x4BD0F02000 4 KB
NAVSS0_VIRT_ALIAS_13_IO_PVU0_CFG_MMRS 0x4BD0F80000 0x4BD0F81000 4 KB
NAVSS0_VIRT_ALIAS_13_IO_PVU1_CFG_MMRS 0x4BD0F81000 0x4BD0F82000 4 KB
NAVSS0_VIRT_ALIAS_13_PVU0_SRC_TOG_CFG 0x4BD0F90000 0x4BD0F90400 1 KB
NAVSS0_VIRT_ALIAS_13_PVU0_CFG_TOG_CFG 0x4BD0F91000 0x4BD0F91400 1 KB
NAVSS0_VIRT_ALIAS_13_ECCAGGR0 0x4BD1000000 0x4BD1000400 1 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_ECCAGGR_CFG 0x4BD1001000 0x4BD1001400 1 KB
NAVSS0_VIRT_ALIAS_13_VIRTSS_ECCAGGR_CFG 0x4BD1002000 0x4BD1002400 1 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_GCNTCFG 0x4BD1040000 0x4BD1044000 16 KB
NAVSS0_VIRT_ALIAS_13_RINGACC0_CFG 0x4BD1080000 0x4BD10C0000 256 KB
NAVSS0_VIRT_ALIAS_13_REGS0_CFG_MMRS 0x4BD10C0000 0x4BD10C0100 256 B
NAVSS0_VIRT_ALIAS_13_CPTS0_S_VBUSP_CPTS_VBUSP 0x4BD10D0000 0x4BD10D0400 1 KB
NAVSS0_VIRT_ALIAS_13_INTR0_CFG_INTR_ROUTER_CFG 0x4BD10E0000 0x4BD10E4000 16 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_L2G 0x4BD1100000 0x4BD1102000 8 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_MCAST 0x4BD1110000 0x4BD1114000 16 KB
NAVSS0_VIRT_ALIAS_13_PROXY0_CFG_BUF_CFG_GCFG 0x4BD1120000 0x4BD1120100 256 B
NAVSS0_VIRT_ALIAS_13_PROXY0_CFG_BUFRAM_SLV_RAM 0x4BD1130000 0x4BD1134000 16 KB
NAVSS0_VIRT_ALIAS_13_SEC_PROXY0_CFG_MMRS 0x4BD1140000 0x4BD1140100 256 B
NAVSS0_VIRT_ALIAS_13_UDMAP0_CFG_GCFG 0x4BD1150000 0x4BD1150100 256 B
NAVSS0_VIRT_ALIAS_13_RINGACC0_CFG_GCFG 0x4BD1160000 0x4BD1160400 1 KB
NAVSS0_VIRT_ALIAS_13_PSILSS0_CFG_MMRS 0x4BD1170000 0x4BD1171000 4 KB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_GCFG 0x4BD11A0000 0x4BD11A0100 256 B
NAVSS0_VIRT_ALIAS_13_MCRC0_S_CFG_MCRC64 0x4BD1F70000 0x4BD1F71000 4 KB
NAVSS0_VIRT_ALIAS_13_PSILCFG0_CFG_PROXY 0x4BD1F78000 0x4BD1F78200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS0 0x4BD1F80000 0x4BD1F80200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS1 0x4BD1F81000 0x4BD1F81200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS2 0x4BD1F82000 0x4BD1F82200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS3 0x4BD1F83000 0x4BD1F83200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS4 0x4BD1F84000 0x4BD1F84200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS5 0x4BD1F85000 0x4BD1F85200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS6 0x4BD1F86000 0x4BD1F86200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS7 0x4BD1F87000 0x4BD1F87200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS8 0x4BD1F88000 0x4BD1F88200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS9 0x4BD1F89000 0x4BD1F89200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS10 0x4BD1F8A000 0x4BD1F8A200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX0_CFG_REGS11 0x4BD1F8B000 0x4BD1F8B200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS0 0x4BD1F90000 0x4BD1F90200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS1 0x4BD1F91000 0x4BD1F91200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS2 0x4BD1F92000 0x4BD1F92200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS3 0x4BD1F93000 0x4BD1F93200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS4 0x4BD1F94000 0x4BD1F94200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS5 0x4BD1F95000 0x4BD1F95200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS6 0x4BD1F96000 0x4BD1F96200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS7 0x4BD1F97000 0x4BD1F97200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS8 0x4BD1F98000 0x4BD1F98200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS9 0x4BD1F99000 0x4BD1F99200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS10 0x4BD1F9A000 0x4BD1F9A200 512 B
NAVSS0_VIRT_ALIAS_13_MAILBOX1_CFG_REGS11 0x4BD1F9B000 0x4BD1F9B200 512 B
NAVSS0_VIRT_ALIAS_13_RINGACC0_CFG_MON 0x4BD2000000 0x4BD2020000 128 KB
NAVSS0_VIRT_ALIAS_13_TIMERMGR0_CFG_TIMERS 0x4BD2200000 0x4BD2240000 256 KB
NAVSS0_VIRT_ALIAS_13_TIMERMGR1_CFG_TIMERS 0x4BD2240000 0x4BD2280000 256 KB
NAVSS0_VIRT_ALIAS_13_SEC_PROXY0_CFG_RT 0x4BD2400000 0x4BD2600000 2 MB
NAVSS0_VIRT_ALIAS_13_SEC_PROXY0_CFG_SCFG 0x4BD2800000 0x4BD2A00000 2 MB
NAVSS0_VIRT_ALIAS_13_SEC_PROXY0_SRC_TARGET_DATA 0x4BD2C00000 0x4BD2E00000 2 MB
NAVSS0_VIRT_ALIAS_13_PROXY0_SRC_TARGET0_DATA 0x4BD3000000 0x4BD3040000 256 KB
NAVSS0_VIRT_ALIAS_13_PROXY0_CFG_BUF_CFG 0x4BD3400000 0x4BD3440000 256 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_GCNTRTI 0x4BD3800000 0x4BD3A00000 2 MB
NAVSS0_VIRT_ALIAS_13_MODSS_INTA0_CFG_INTR 0x4BD3C00000 0x4BD3C40000 256 KB
NAVSS0_VIRT_ALIAS_13_MODSS_INTA1_CFG_INTR 0x4BD3C40000 0x4BD3C80000 256 KB
NAVSS0_VIRT_ALIAS_13_UDMASS_INTA0_CFG_INTR 0x4BD3D00000 0x4BD3E00000 1 MB
NAVSS0_VIRT_ALIAS_13_UDMAP0_CFG_RCHANRT 0x4BD4000000 0x4BD4080000 512 KB
NAVSS0_VIRT_ALIAS_13_UDMAP0_CFG_TCHANRT 0x4BD5000000 0x4BD5200000 2 MB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_TCHAN 0x4BD5840000 0x4BD5841000 4 KB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_RCHAN 0x4BD5880000 0x4BD5882000 8 KB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_RING 0x4BD5900000 0x4BD5904000 16 KB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_TCHANRT 0x4BD5C00000 0x4BD5C10000 64 KB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_RCHANRT 0x4BD5D00000 0x4BD5D20000 128 KB
NAVSS0_VIRT_ALIAS_13_BCDMA0_CFG_RINGRT 0x4BD5E00000 0x4BD5E80000 512 KB
NAVSS0_VIRT_ALIAS_13_IO_PVU0_CFG_TLBIF_TLB 0x4BD6000000 0x4BD6040000 256 KB
NAVSS0_VIRT_ALIAS_13_IO_PVU1_CFG_TLBIF_TLB 0x4BD6040000 0x4BD6080000 256 KB
NAVSS0_VIRT_ALIAS_13_RINGACC0_SRC_FIFOS 0x4BD8000000 0x4BD8400000 4 MB
NAVSS0_VIRT_ALIAS_13_RINGACC0_CFG_RT 0x4BDC000000 0x4BDC400000 4 MB
NAVSS0_VIRT_ALIAS_14_MODSS_INTA0_CFG 0x4BE0800000 0x4BE0800020 32 B
NAVSS0_VIRT_ALIAS_14_MODSS_INTA1_CFG 0x4BE0801000 0x4BE0801020 32 B
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG 0x4BE0802000 0x4BE0802020 32 B
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_UNMAP 0x4BE0880000 0x4BE0890000 64 KB
NAVSS0_VIRT_ALIAS_14_MODSS_INTA0_CFG_IMAP 0x4BE0900000 0x4BE0902000 8 KB
NAVSS0_VIRT_ALIAS_14_MODSS_INTA1_CFG_IMAP 0x4BE0908000 0x4BE090A000 8 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_IMAP 0x4BE0940000 0x4BE0950000 64 KB
NAVSS0_VIRT_ALIAS_14_NAV_DDR0_VIRTID_CFG_MMRS 0x4BE0A02000 0x4BE0A02100 256 B
NAVSS0_VIRT_ALIAS_14_NAV_DDR1_VIRTID_CFG_MMRS 0x4BE0A03000 0x4BE0A03100 256 B
NAVSS0_VIRT_ALIAS_14_UDMAP0_CFG_TCHAN 0x4BE0B00000 0x4BE0B20000 128 KB
NAVSS0_VIRT_ALIAS_14_UDMAP0_CFG_RCHAN 0x4BE0C00000 0x4BE0C08000 32 KB
NAVSS0_VIRT_ALIAS_14_UDMAP0_CFG_RFLOW 0x4BE0D00000 0x4BE0D04000 16 KB
NAVSS0_VIRT_ALIAS_14_SPINLOCK0_CFG 0x4BE0E00000 0x4BE0E08000 32 KB
NAVSS0_VIRT_ALIAS_14_TIMERMGR0_CFG_CONFIG 0x4BE0E80000 0x4BE0E80200 512 B
NAVSS0_VIRT_ALIAS_14_TIMERMGR1_CFG_CONFIG 0x4BE0E81000 0x4BE0E81200 512 B
NAVSS0_VIRT_ALIAS_14_TIMERMGR0_CFG_OES 0x4BE0F00000 0x4BE0F01000 4 KB
NAVSS0_VIRT_ALIAS_14_TIMERMGR1_CFG_OES 0x4BE0F01000 0x4BE0F02000 4 KB
NAVSS0_VIRT_ALIAS_14_IO_PVU0_CFG_MMRS 0x4BE0F80000 0x4BE0F81000 4 KB
NAVSS0_VIRT_ALIAS_14_IO_PVU1_CFG_MMRS 0x4BE0F81000 0x4BE0F82000 4 KB
NAVSS0_VIRT_ALIAS_14_PVU0_SRC_TOG_CFG 0x4BE0F90000 0x4BE0F90400 1 KB
NAVSS0_VIRT_ALIAS_14_PVU0_CFG_TOG_CFG 0x4BE0F91000 0x4BE0F91400 1 KB
NAVSS0_VIRT_ALIAS_14_ECCAGGR0 0x4BE1000000 0x4BE1000400 1 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_ECCAGGR_CFG 0x4BE1001000 0x4BE1001400 1 KB
NAVSS0_VIRT_ALIAS_14_VIRTSS_ECCAGGR_CFG 0x4BE1002000 0x4BE1002400 1 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_GCNTCFG 0x4BE1040000 0x4BE1044000 16 KB
NAVSS0_VIRT_ALIAS_14_RINGACC0_CFG 0x4BE1080000 0x4BE10C0000 256 KB
NAVSS0_VIRT_ALIAS_14_REGS0_CFG_MMRS 0x4BE10C0000 0x4BE10C0100 256 B
NAVSS0_VIRT_ALIAS_14_CPTS0_S_VBUSP_CPTS_VBUSP 0x4BE10D0000 0x4BE10D0400 1 KB
NAVSS0_VIRT_ALIAS_14_INTR0_CFG_INTR_ROUTER_CFG 0x4BE10E0000 0x4BE10E4000 16 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_L2G 0x4BE1100000 0x4BE1102000 8 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_MCAST 0x4BE1110000 0x4BE1114000 16 KB
NAVSS0_VIRT_ALIAS_14_PROXY0_CFG_BUF_CFG_GCFG 0x4BE1120000 0x4BE1120100 256 B
NAVSS0_VIRT_ALIAS_14_PROXY0_CFG_BUFRAM_SLV_RAM 0x4BE1130000 0x4BE1134000 16 KB
NAVSS0_VIRT_ALIAS_14_SEC_PROXY0_CFG_MMRS 0x4BE1140000 0x4BE1140100 256 B
NAVSS0_VIRT_ALIAS_14_UDMAP0_CFG_GCFG 0x4BE1150000 0x4BE1150100 256 B
NAVSS0_VIRT_ALIAS_14_RINGACC0_CFG_GCFG 0x4BE1160000 0x4BE1160400 1 KB
NAVSS0_VIRT_ALIAS_14_PSILSS0_CFG_MMRS 0x4BE1170000 0x4BE1171000 4 KB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_GCFG 0x4BE11A0000 0x4BE11A0100 256 B
NAVSS0_VIRT_ALIAS_14_MCRC0_S_CFG_MCRC64 0x4BE1F70000 0x4BE1F71000 4 KB
NAVSS0_VIRT_ALIAS_14_PSILCFG0_CFG_PROXY 0x4BE1F78000 0x4BE1F78200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS0 0x4BE1F80000 0x4BE1F80200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS1 0x4BE1F81000 0x4BE1F81200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS2 0x4BE1F82000 0x4BE1F82200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS3 0x4BE1F83000 0x4BE1F83200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS4 0x4BE1F84000 0x4BE1F84200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS5 0x4BE1F85000 0x4BE1F85200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS6 0x4BE1F86000 0x4BE1F86200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS7 0x4BE1F87000 0x4BE1F87200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS8 0x4BE1F88000 0x4BE1F88200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS9 0x4BE1F89000 0x4BE1F89200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS10 0x4BE1F8A000 0x4BE1F8A200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX0_CFG_REGS11 0x4BE1F8B000 0x4BE1F8B200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS0 0x4BE1F90000 0x4BE1F90200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS1 0x4BE1F91000 0x4BE1F91200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS2 0x4BE1F92000 0x4BE1F92200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS3 0x4BE1F93000 0x4BE1F93200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS4 0x4BE1F94000 0x4BE1F94200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS5 0x4BE1F95000 0x4BE1F95200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS6 0x4BE1F96000 0x4BE1F96200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS7 0x4BE1F97000 0x4BE1F97200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS8 0x4BE1F98000 0x4BE1F98200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS9 0x4BE1F99000 0x4BE1F99200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS10 0x4BE1F9A000 0x4BE1F9A200 512 B
NAVSS0_VIRT_ALIAS_14_MAILBOX1_CFG_REGS11 0x4BE1F9B000 0x4BE1F9B200 512 B
NAVSS0_VIRT_ALIAS_14_RINGACC0_CFG_MON 0x4BE2000000 0x4BE2020000 128 KB
NAVSS0_VIRT_ALIAS_14_TIMERMGR0_CFG_TIMERS 0x4BE2200000 0x4BE2240000 256 KB
NAVSS0_VIRT_ALIAS_14_TIMERMGR1_CFG_TIMERS 0x4BE2240000 0x4BE2280000 256 KB
NAVSS0_VIRT_ALIAS_14_SEC_PROXY0_CFG_RT 0x4BE2400000 0x4BE2600000 2 MB
NAVSS0_VIRT_ALIAS_14_SEC_PROXY0_CFG_SCFG 0x4BE2800000 0x4BE2A00000 2 MB
NAVSS0_VIRT_ALIAS_14_SEC_PROXY0_SRC_TARGET_DATA 0x4BE2C00000 0x4BE2E00000 2 MB
NAVSS0_VIRT_ALIAS_14_PROXY0_SRC_TARGET0_DATA 0x4BE3000000 0x4BE3040000 256 KB
NAVSS0_VIRT_ALIAS_14_PROXY0_CFG_BUF_CFG 0x4BE3400000 0x4BE3440000 256 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_GCNTRTI 0x4BE3800000 0x4BE3A00000 2 MB
NAVSS0_VIRT_ALIAS_14_MODSS_INTA0_CFG_INTR 0x4BE3C00000 0x4BE3C40000 256 KB
NAVSS0_VIRT_ALIAS_14_MODSS_INTA1_CFG_INTR 0x4BE3C40000 0x4BE3C80000 256 KB
NAVSS0_VIRT_ALIAS_14_UDMASS_INTA0_CFG_INTR 0x4BE3D00000 0x4BE3E00000 1 MB
NAVSS0_VIRT_ALIAS_14_UDMAP0_CFG_RCHANRT 0x4BE4000000 0x4BE4080000 512 KB
NAVSS0_VIRT_ALIAS_14_UDMAP0_CFG_TCHANRT 0x4BE5000000 0x4BE5200000 2 MB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_TCHAN 0x4BE5840000 0x4BE5841000 4 KB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_RCHAN 0x4BE5880000 0x4BE5882000 8 KB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_RING 0x4BE5900000 0x4BE5904000 16 KB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_TCHANRT 0x4BE5C00000 0x4BE5C10000 64 KB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_RCHANRT 0x4BE5D00000 0x4BE5D20000 128 KB
NAVSS0_VIRT_ALIAS_14_BCDMA0_CFG_RINGRT 0x4BE5E00000 0x4BE5E80000 512 KB
NAVSS0_VIRT_ALIAS_14_IO_PVU0_CFG_TLBIF_TLB 0x4BE6000000 0x4BE6040000 256 KB
NAVSS0_VIRT_ALIAS_14_IO_PVU1_CFG_TLBIF_TLB 0x4BE6040000 0x4BE6080000 256 KB
NAVSS0_VIRT_ALIAS_14_RINGACC0_SRC_FIFOS 0x4BE8000000 0x4BE8400000 4 MB
NAVSS0_VIRT_ALIAS_14_RINGACC0_CFG_RT 0x4BEC000000 0x4BEC400000 4 MB
NAVSS0_VIRT_ALIAS_15_MODSS_INTA0_CFG 0x4BF0800000 0x4BF0800020 32 B
NAVSS0_VIRT_ALIAS_15_MODSS_INTA1_CFG 0x4BF0801000 0x4BF0801020 32 B
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG 0x4BF0802000 0x4BF0802020 32 B
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_UNMAP 0x4BF0880000 0x4BF0890000 64 KB
NAVSS0_VIRT_ALIAS_15_MODSS_INTA0_CFG_IMAP 0x4BF0900000 0x4BF0902000 8 KB
NAVSS0_VIRT_ALIAS_15_MODSS_INTA1_CFG_IMAP 0x4BF0908000 0x4BF090A000 8 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_IMAP 0x4BF0940000 0x4BF0950000 64 KB
NAVSS0_VIRT_ALIAS_15_NAV_DDR0_VIRTID_CFG_MMRS 0x4BF0A02000 0x4BF0A02100 256 B
NAVSS0_VIRT_ALIAS_15_NAV_DDR1_VIRTID_CFG_MMRS 0x4BF0A03000 0x4BF0A03100 256 B
NAVSS0_VIRT_ALIAS_15_UDMAP0_CFG_TCHAN 0x4BF0B00000 0x4BF0B20000 128 KB
NAVSS0_VIRT_ALIAS_15_UDMAP0_CFG_RCHAN 0x4BF0C00000 0x4BF0C08000 32 KB
NAVSS0_VIRT_ALIAS_15_UDMAP0_CFG_RFLOW 0x4BF0D00000 0x4BF0D04000 16 KB
NAVSS0_VIRT_ALIAS_15_SPINLOCK0_CFG 0x4BF0E00000 0x4BF0E08000 32 KB
NAVSS0_VIRT_ALIAS_15_TIMERMGR0_CFG_CONFIG 0x4BF0E80000 0x4BF0E80200 512 B
NAVSS0_VIRT_ALIAS_15_TIMERMGR1_CFG_CONFIG 0x4BF0E81000 0x4BF0E81200 512 B
NAVSS0_VIRT_ALIAS_15_TIMERMGR0_CFG_OES 0x4BF0F00000 0x4BF0F01000 4 KB
NAVSS0_VIRT_ALIAS_15_TIMERMGR1_CFG_OES 0x4BF0F01000 0x4BF0F02000 4 KB
NAVSS0_VIRT_ALIAS_15_IO_PVU0_CFG_MMRS 0x4BF0F80000 0x4BF0F81000 4 KB
NAVSS0_VIRT_ALIAS_15_IO_PVU1_CFG_MMRS 0x4BF0F81000 0x4BF0F82000 4 KB
NAVSS0_VIRT_ALIAS_15_PVU0_SRC_TOG_CFG 0x4BF0F90000 0x4BF0F90400 1 KB
NAVSS0_VIRT_ALIAS_15_PVU0_CFG_TOG_CFG 0x4BF0F91000 0x4BF0F91400 1 KB
NAVSS0_VIRT_ALIAS_15_ECCAGGR0 0x4BF1000000 0x4BF1000400 1 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_ECCAGGR_CFG 0x4BF1001000 0x4BF1001400 1 KB
NAVSS0_VIRT_ALIAS_15_VIRTSS_ECCAGGR_CFG 0x4BF1002000 0x4BF1002400 1 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_GCNTCFG 0x4BF1040000 0x4BF1044000 16 KB
NAVSS0_VIRT_ALIAS_15_RINGACC0_CFG 0x4BF1080000 0x4BF10C0000 256 KB
NAVSS0_VIRT_ALIAS_15_REGS0_CFG_MMRS 0x4BF10C0000 0x4BF10C0100 256 B
NAVSS0_VIRT_ALIAS_15_CPTS0_S_VBUSP_CPTS_VBUSP 0x4BF10D0000 0x4BF10D0400 1 KB
NAVSS0_VIRT_ALIAS_15_INTR0_CFG_INTR_ROUTER_CFG 0x4BF10E0000 0x4BF10E4000 16 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_L2G 0x4BF1100000 0x4BF1102000 8 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_MCAST 0x4BF1110000 0x4BF1114000 16 KB
NAVSS0_VIRT_ALIAS_15_PROXY0_CFG_BUF_CFG_GCFG 0x4BF1120000 0x4BF1120100 256 B
NAVSS0_VIRT_ALIAS_15_PROXY0_CFG_BUFRAM_SLV_RAM 0x4BF1130000 0x4BF1134000 16 KB
NAVSS0_VIRT_ALIAS_15_SEC_PROXY0_CFG_MMRS 0x4BF1140000 0x4BF1140100 256 B
NAVSS0_VIRT_ALIAS_15_UDMAP0_CFG_GCFG 0x4BF1150000 0x4BF1150100 256 B
NAVSS0_VIRT_ALIAS_15_RINGACC0_CFG_GCFG 0x4BF1160000 0x4BF1160400 1 KB
NAVSS0_VIRT_ALIAS_15_PSILSS0_CFG_MMRS 0x4BF1170000 0x4BF1171000 4 KB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_GCFG 0x4BF11A0000 0x4BF11A0100 256 B
NAVSS0_VIRT_ALIAS_15_MCRC0_S_CFG_MCRC64 0x4BF1F70000 0x4BF1F71000 4 KB
NAVSS0_VIRT_ALIAS_15_PSILCFG0_CFG_PROXY 0x4BF1F78000 0x4BF1F78200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS0 0x4BF1F80000 0x4BF1F80200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS1 0x4BF1F81000 0x4BF1F81200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS2 0x4BF1F82000 0x4BF1F82200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS3 0x4BF1F83000 0x4BF1F83200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS4 0x4BF1F84000 0x4BF1F84200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS5 0x4BF1F85000 0x4BF1F85200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS6 0x4BF1F86000 0x4BF1F86200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS7 0x4BF1F87000 0x4BF1F87200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS8 0x4BF1F88000 0x4BF1F88200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS9 0x4BF1F89000 0x4BF1F89200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS10 0x4BF1F8A000 0x4BF1F8A200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX0_CFG_REGS11 0x4BF1F8B000 0x4BF1F8B200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS0 0x4BF1F90000 0x4BF1F90200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS1 0x4BF1F91000 0x4BF1F91200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS2 0x4BF1F92000 0x4BF1F92200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS3 0x4BF1F93000 0x4BF1F93200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS4 0x4BF1F94000 0x4BF1F94200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS5 0x4BF1F95000 0x4BF1F95200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS6 0x4BF1F96000 0x4BF1F96200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS7 0x4BF1F97000 0x4BF1F97200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS8 0x4BF1F98000 0x4BF1F98200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS9 0x4BF1F99000 0x4BF1F99200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS10 0x4BF1F9A000 0x4BF1F9A200 512 B
NAVSS0_VIRT_ALIAS_15_MAILBOX1_CFG_REGS11 0x4BF1F9B000 0x4BF1F9B200 512 B
NAVSS0_VIRT_ALIAS_15_RINGACC0_CFG_MON 0x4BF2000000 0x4BF2020000 128 KB
NAVSS0_VIRT_ALIAS_15_TIMERMGR0_CFG_TIMERS 0x4BF2200000 0x4BF2240000 256 KB
NAVSS0_VIRT_ALIAS_15_TIMERMGR1_CFG_TIMERS 0x4BF2240000 0x4BF2280000 256 KB
NAVSS0_VIRT_ALIAS_15_SEC_PROXY0_CFG_RT 0x4BF2400000 0x4BF2600000 2 MB
NAVSS0_VIRT_ALIAS_15_SEC_PROXY0_CFG_SCFG 0x4BF2800000 0x4BF2A00000 2 MB
NAVSS0_VIRT_ALIAS_15_SEC_PROXY0_SRC_TARGET_DATA 0x4BF2C00000 0x4BF2E00000 2 MB
NAVSS0_VIRT_ALIAS_15_PROXY0_SRC_TARGET0_DATA 0x4BF3000000 0x4BF3040000 256 KB
NAVSS0_VIRT_ALIAS_15_PROXY0_CFG_BUF_CFG 0x4BF3400000 0x4BF3440000 256 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_GCNTRTI 0x4BF3800000 0x4BF3A00000 2 MB
NAVSS0_VIRT_ALIAS_15_MODSS_INTA0_CFG_INTR 0x4BF3C00000 0x4BF3C40000 256 KB
NAVSS0_VIRT_ALIAS_15_MODSS_INTA1_CFG_INTR 0x4BF3C40000 0x4BF3C80000 256 KB
NAVSS0_VIRT_ALIAS_15_UDMASS_INTA0_CFG_INTR 0x4BF3D00000 0x4BF3E00000 1 MB
NAVSS0_VIRT_ALIAS_15_UDMAP0_CFG_RCHANRT 0x4BF4000000 0x4BF4080000 512 KB
NAVSS0_VIRT_ALIAS_15_UDMAP0_CFG_TCHANRT 0x4BF5000000 0x4BF5200000 2 MB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_TCHAN 0x4BF5840000 0x4BF5841000 4 KB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_RCHAN 0x4BF5880000 0x4BF5882000 8 KB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_RING 0x4BF5900000 0x4BF5904000 16 KB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_TCHANRT 0x4BF5C00000 0x4BF5C10000 64 KB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_RCHANRT 0x4BF5D00000 0x4BF5D20000 128 KB
NAVSS0_VIRT_ALIAS_15_BCDMA0_CFG_RINGRT 0x4BF5E00000 0x4BF5E80000 512 KB
NAVSS0_VIRT_ALIAS_15_IO_PVU0_CFG_TLBIF_TLB 0x4BF6000000 0x4BF6040000 256 KB
NAVSS0_VIRT_ALIAS_15_IO_PVU1_CFG_TLBIF_TLB 0x4BF6040000 0x4BF6080000 256 KB
NAVSS0_VIRT_ALIAS_15_RINGACC0_SRC_FIFOS 0x4BF8000000 0x4BF8400000 4 MB
NAVSS0_VIRT_ALIAS_15_RINGACC0_CFG_RT 0x4BFC000000 0x4BFC400000 4 MB
DEBUGSS_WRAP0_ROM_TABLE_0_0 0x4C00000000 0x4C00001000 4 KB
DEBUGSS_WRAP0_RESV0_0 0x4C00001000 0x4C00002000 4 KB
DEBUGSS_WRAP0_CFGAP0 0x4C00002000 0x4C00002100 256 B
DEBUGSS_WRAP0_APBAP0 0x4C00002100 0x4C00002200 256 B
DEBUGSS_WRAP0_AXIAP0 0x4C00002200 0x4C00002300 256 B
DEBUGSS_WRAP0_PWRAP0 0x4C00002300 0x4C00002400 256 B
DEBUGSS_WRAP0_PVIEW0 0x4C00002400 0x4C00002500 256 B
DEBUGSS_WRAP0_JTAGAP0 0x4C00002500 0x4C00002600 256 B
DEBUGSS_WRAP0_SECAP0 0x4C00002600 0x4C00002700 256 B
DEBUGSS_WRAP0_CORTEX0_CFG0 0x4C00002700 0x4C00002800 256 B
DEBUGSS_WRAP0_CORTEX1_CFG0 0x4C00002800 0x4C00002900 256 B
DEBUGSS_WRAP0_CORTEX2_CFG0 0x4C00002900 0x4C00002A00 256 B
DEBUGSS_WRAP0_CORTEX3_CFG0 0x4C00002A00 0x4C00002B00 256 B
DEBUGSS_WRAP0_CORTEX4_CFG0 0x4C00002B00 0x4C00002C00 256 B
DEBUGSS_WRAP0_CORTEX5_CFG0 0x4C00002C00 0x4C00002D00 256 B
DEBUGSS_WRAP0_CORTEX6_CFG0 0x4C00002D00 0x4C00002E00 256 B
DEBUGSS_WRAP0_CORTEX7_CFG0 0x4C00002E00 0x4C00002F00 256 B
DEBUGSS_WRAP0_CORTEX8_CFG0 0x4C00002F00 0x4C00003000 256 B
DEBUGSS_WRAP0_RESV1_0 0x4C00003000 0x4C00004000 4 KB
DEBUGSS_WRAP0_RESV2_0 0x4C00004000 0x4C02004000 32 MB
DEBUGSS_WRAP0_ROM_TABLE_1_0 0x4C20000000 0x4C20001000 4 KB
DEBUGSS_WRAP0_CSCTI0 0x4C20001000 0x4C20002000 4 KB
DEBUGSS_WRAP0_DRM0 0x4C20002000 0x4C20003000 4 KB
DEBUGSS_WRAP0_RESV3_0 0x4C20003000 0x4C20004000 4 KB
DEBUGSS_WRAP0_CSTPIU0 0x4C20004000 0x4C20005000 4 KB
DEBUGSS_WRAP0_CTF0 0x4C20005000 0x4C20006000 4 KB
DEBUGSS_WRAP0_RESV4_0 0x4C20006000 0x4C21006000 16 MB
DEBUGSS_WRAP0_EXT_APB0 0x4C30000000 0x4C40000000 256 MB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CCROM_DBG_CCROM 0x4C30000000 0x4C30001000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_CCROM_DBG_CCROM 0x4C30004000 0x4C30005000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_CCROM_DBG_CCROM 0x4C30005000 0x4C30006000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_CCROM_DBG_CCROM 0x4C30006000 0x4C30007000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_CCROM_DBG_CCROM 0x4C30007000 0x4C30008000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTSET_DBG_CTSET 0x4C30100000 0x4C30102000 8 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI0_DBG_CTI0 0x4C30102000 0x4C30103000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI1_DBG_CTI1 0x4C30103000 0x4C30104000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI2_DBG_CTI2 0x4C30104000 0x4C30105000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI3_DBG_CTI3 0x4C30105000 0x4C30106000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI4_DBG_CTI4 0x4C30106000 0x4C30107000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI5_DBG_CTI5 0x4C30107000 0x4C30108000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI7_DBG_CTI7 0x4C30109000 0x4C3010A000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CTI8_DBG_CTI8 0x4C3010A000 0x4C3010B000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_AGR0_DBG_AGR0 0x4C30140000 0x4C30180000 256 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_AGR1_DBG_AGR1 0x4C30180000 0x4C301C0000 256 KB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CPAC0_DBG_CPAC0 0x4C30400000 0x4C30800000 4 MB
COMPUTE_CLUSTERHP0_VBUSP_DBG_CPAC1_DBG_CPAC1 0x4C30800000 0x4C30C00000 4 MB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_CPAC0_DBG_CPAC0 0x4C31400000 0x4C31800000 4 MB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_CPAC0_DBG_CPAC0 0x4C31800000 0x4C31C00000 4 MB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_CPAC0_DBG_CPAC0 0x4C31C00000 0x4C32000000 4 MB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_CPAC0_DBG_CPAC0 0x4C32000000 0x4C32400000 4 MB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_CTSET_DBG_CTSET 0x4C33000000 0x4C33002000 8 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_CTI0_DBG_CTI0 0x4C33002000 0x4C33003000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_CTI1_DBG_CTI1 0x4C33003000 0x4C33004000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_CTI2_DBG_CTI2 0x4C33004000 0x4C33005000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_4_VBUSP_DBG_AGR0_DBG_AGR0 0x4C33040000 0x4C33080000 256 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_CTSET_DBG_CTSET 0x4C33100000 0x4C33102000 8 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_CTI0_DBG_CTI0 0x4C33102000 0x4C33103000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_CTI1_DBG_CTI1 0x4C33103000 0x4C33104000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_CTI2_DBG_CTI2 0x4C33104000 0x4C33105000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_5_VBUSP_DBG_AGR0_DBG_AGR0 0x4C33140000 0x4C33180000 256 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_CTSET_DBG_CTSET 0x4C33200000 0x4C33202000 8 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_CTI0_DBG_CTI0 0x4C33202000 0x4C33203000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_CTI1_DBG_CTI1 0x4C33203000 0x4C33204000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_CTI2_DBG_CTI2 0x4C33204000 0x4C33205000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_6_VBUSP_DBG_AGR0_DBG_AGR0 0x4C33240000 0x4C33280000 256 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_CTSET_DBG_CTSET 0x4C33300000 0x4C33302000 8 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_CTI0_DBG_CTI0 0x4C33302000 0x4C33303000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_CTI1_DBG_CTI1 0x4C33303000 0x4C33304000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_CTI2_DBG_CTI2 0x4C33304000 0x4C33305000 4 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG_AN_7_VBUSP_DBG_AGR0_DBG_AGR0 0x4C33340000 0x4C33380000 256 KB
CCDEBUGSS0_ROM 0x4C3C000000 0x4C3C001000 4 KB
CCDEBUGSS0_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG 0x4C3C004000 0x4C3C005000 4 KB
CCDEBUGSS0_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG 0x4C3C005000 0x4C3C006000 4 KB
CCDEBUGSS0_ARM_CTI_0_CFG_CSCTI_CFG 0x4C3C006000 0x4C3C007000 4 KB
CCDEBUGSS0_ARM_CTI_1_CFG_CSCTI_CFG 0x4C3C008000 0x4C3C009000 4 KB
CCDEBUGSS0_ARM_CTI_2_CFG_CSCTI_CFG 0x4C3C009000 0x4C3C00A000 4 KB
CCDEBUGSS0_ARM_CTI_3_CFG_CSCTI_CFG 0x4C3C00A000 0x4C3C00B000 4 KB
CCDEBUGSS0_ARM_CTI_4_CFG_CSCTI_CFG 0x4C3C00B000 0x4C3C00C000 4 KB
CCDEBUGSS0_ARM_CTI_5_CFG_CSCTI_CFG 0x4C3C00C000 0x4C3C00D000 4 KB
CCDEBUGSS0_ARM_CTI_6_CFG_CSCTI_CFG 0x4C3C00D000 0x4C3C00E000 4 KB
CCDEBUGSS0_ARM_CTI_7_CFG_CSCTI_CFG 0x4C3C00E000 0x4C3C00F000 4 KB
CCDEBUGSS0_ARM_CTI_8_CFG_CSCTI_CFG 0x4C3C00F000 0x4C3C010000 4 KB
CCDEBUGSS1_ROM 0x4C3C010000 0x4C3C011000 4 KB
CCDEBUGSS1_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG 0x4C3C014000 0x4C3C015000 4 KB
CCDEBUGSS1_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG 0x4C3C015000 0x4C3C016000 4 KB
CCDEBUGSS1_ARM_CTI_0_CFG_CSCTI_CFG 0x4C3C016000 0x4C3C017000 4 KB
CCDEBUGSS1_ARM_CTI_1_CFG_CSCTI_CFG 0x4C3C018000 0x4C3C019000 4 KB
CCDEBUGSS1_ARM_CTI_2_CFG_CSCTI_CFG 0x4C3C019000 0x4C3C01A000 4 KB
CCDEBUGSS1_ARM_CTI_3_CFG_CSCTI_CFG 0x4C3C01A000 0x4C3C01B000 4 KB
CCDEBUGSS1_ARM_CTI_4_CFG_CSCTI_CFG 0x4C3C01B000 0x4C3C01C000 4 KB
CCDEBUGSS1_ARM_CTI_5_CFG_CSCTI_CFG 0x4C3C01C000 0x4C3C01D000 4 KB
CCDEBUGSS1_ARM_CTI_6_CFG_CSCTI_CFG 0x4C3C01D000 0x4C3C01E000 4 KB
CCDEBUGSS1_ARM_CTI_7_CFG_CSCTI_CFG 0x4C3C01E000 0x4C3C01F000 4 KB
CCDEBUGSS1_ARM_CTI_8_CFG_CSCTI_CFG 0x4C3C01F000 0x4C3C020000 4 KB
DEBUGSS0_ROM 0x4C3C020000 0x4C3C021000 4 KB
DEBUGSS0_CTSET2_WRAP_CFG_CTSET2_CFG 0x4C3C022000 0x4C3C024000 8 KB
DEBUGSS0_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG 0x4C3C024000 0x4C3C025000 4 KB
DEBUGSS0_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG 0x4C3C025000 0x4C3C026000 4 KB
DEBUGSS0_ARM_CTI_0_CFG_CSCTI_CFG 0x4C3C026000 0x4C3C027000 4 KB
DEBUGSS0_ARM_CTI_1_CFG_CSCTI_CFG 0x4C3C028000 0x4C3C029000 4 KB
DEBUGSS0_ARM_CTI_2_CFG_CSCTI_CFG 0x4C3C029000 0x4C3C02A000 4 KB
DEBUGSS0_ARM_CTI_3_CFG_CSCTI_CFG 0x4C3C02A000 0x4C3C02B000 4 KB
DEBUGSS0_ARM_CTI_4_CFG_CSCTI_CFG 0x4C3C02B000 0x4C3C02C000 4 KB
DEBUGSS0_ARM_CTI_5_CFG_CSCTI_CFG 0x4C3C02C000 0x4C3C02D000 4 KB
DEBUGSS0_ARM_CTI_6_CFG_CSCTI_CFG 0x4C3C02D000 0x4C3C02E000 4 KB
DEBUGSS0_ARM_CTI_7_CFG_CSCTI_CFG 0x4C3C02E000 0x4C3C02F000 4 KB
DEBUGSS0_ARM_CTI_8_CFG_CSCTI_CFG 0x4C3C02F000 0x4C3C030000 4 KB
CCDEBUGSS2_ROM 0x4C3C030000 0x4C3C031000 4 KB
CCDEBUGSS2_ATB_REPLICATOR_CFG_CXATBREPLICATOR_CFG 0x4C3C034000 0x4C3C035000 4 KB
CCDEBUGSS2_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG 0x4C3C035000 0x4C3C036000 4 KB
CCDEBUGSS2_ARM_CTI_0_CFG_CSCTI_CFG 0x4C3C036000 0x4C3C037000 4 KB
CCDEBUGSS2_ARM_CTI_1_CFG_CSCTI_CFG 0x4C3C038000 0x4C3C039000 4 KB
CCDEBUGSS2_ARM_CTI_2_CFG_CSCTI_CFG 0x4C3C039000 0x4C3C03A000 4 KB
CCDEBUGSS2_ARM_CTI_3_CFG_CSCTI_CFG 0x4C3C03A000 0x4C3C03B000 4 KB
CCDEBUGSS2_ARM_CTI_4_CFG_CSCTI_CFG 0x4C3C03B000 0x4C3C03C000 4 KB
CCDEBUGSS2_ARM_CTI_5_CFG_CSCTI_CFG 0x4C3C03C000 0x4C3C03D000 4 KB
CCDEBUGSS2_ARM_CTI_6_CFG_CSCTI_CFG 0x4C3C03D000 0x4C3C03E000 4 KB
CCDEBUGSS2_ARM_CTI_7_CFG_CSCTI_CFG 0x4C3C03E000 0x4C3C03F000 4 KB
CCDEBUGSS2_ARM_CTI_8_CFG_CSCTI_CFG 0x4C3C03F000 0x4C3C040000 4 KB
STM0_CXSTM 0x4C3D200000 0x4C3D201000 4 KB
STM0_CTI_CSCTI 0x4C3D201000 0x4C3D202000 4 KB
DEBUGSUSPENDRTR0_INTR_ROUTER_CFG 0x4C3D300000 0x4C3D302000 8 KB
CPT2_AGGR0_MMR 0x4C3E100000 0x4C3E100100 256 B
CPT2_AGGR0_STP2ATB_CFG 0x4C3E100100 0x4C3E100200 256 B
CPT2_AGGR0_MEM0 0x4C3E120000 0x4C3E121000 4 KB
CPT2_AGGR0_MEM1 0x4C3E121000 0x4C3E122000 4 KB
CPT2_AGGR0_MEM2 0x4C3E122000 0x4C3E123000 4 KB
CPT2_AGGR0_MEM3 0x4C3E123000 0x4C3E124000 4 KB
CPT2_AGGR0_MEM4 0x4C3E124000 0x4C3E125000 4 KB
CPT2_AGGR0_MEM5 0x4C3E125000 0x4C3E126000 4 KB
CPT2_AGGR0_MEM6 0x4C3E126000 0x4C3E127000 4 KB
CPT2_AGGR0_MEM7 0x4C3E127000 0x4C3E128000 4 KB
CPT2_AGGR0_MEM8 0x4C3E128000 0x4C3E129000 4 KB
CPT2_AGGR0_MEM9 0x4C3E129000 0x4C3E12A000 4 KB
CPT2_AGGR0_MEM10 0x4C3E12A000 0x4C3E12B000 4 KB
CPT2_AGGR0_MEM11 0x4C3E12B000 0x4C3E12C000 4 KB
CPT2_AGGR0_MEM12 0x4C3E12C000 0x4C3E12D000 4 KB
CPT2_AGGR0_MEM13 0x4C3E12D000 0x4C3E12E000 4 KB
CPT2_AGGR0_MEM14 0x4C3E12E000 0x4C3E12F000 4 KB
CPT2_AGGR0_MEM15 0x4C3E12F000 0x4C3E130000 4 KB
CPT2_AGGR0_MEM16 0x4C3E130000 0x4C3E131000 4 KB
CPT2_AGGR0_MEM17 0x4C3E131000 0x4C3E132000 4 KB
CPT2_AGGR0_MEM18 0x4C3E132000 0x4C3E133000 4 KB
CPT2_AGGR0_MEM19 0x4C3E133000 0x4C3E134000 4 KB
CPT2_AGGR0_MEM20 0x4C3E134000 0x4C3E135000 4 KB
CPT2_AGGR0_MEM21 0x4C3E135000 0x4C3E136000 4 KB
CPT2_AGGR0_MEM22 0x4C3E136000 0x4C3E137000 4 KB
CPT2_AGGR0_MEM23 0x4C3E137000 0x4C3E138000 4 KB
CPT2_AGGR0_MEM24 0x4C3E138000 0x4C3E139000 4 KB
CPT2_AGGR0_MEM25 0x4C3E139000 0x4C3E13A000 4 KB
CPT2_AGGR0_MEM26 0x4C3E13A000 0x4C3E13B000 4 KB
CPT2_AGGR0_MEM27 0x4C3E13B000 0x4C3E13C000 4 KB
CPT2_AGGR0_MEM28 0x4C3E13C000 0x4C3E13D000 4 KB
CPT2_AGGR0_MEM29 0x4C3E13D000 0x4C3E13E000 4 KB
CPT2_AGGR0_MEM30 0x4C3E13E000 0x4C3E13F000 4 KB
CPT2_AGGR0_MEM31 0x4C3E13F000 0x4C3E140000 4 KB
CPT2_AGGR4_MMR 0x4C3E140000 0x4C3E140100 256 B
CPT2_AGGR4_STP2ATB_CFG 0x4C3E140100 0x4C3E140200 256 B
CPT2_AGGR4_MEM0 0x4C3E160000 0x4C3E161000 4 KB
CPT2_AGGR4_MEM1 0x4C3E161000 0x4C3E162000 4 KB
CPT2_AGGR4_MEM2 0x4C3E162000 0x4C3E163000 4 KB
CPT2_AGGR4_MEM3 0x4C3E163000 0x4C3E164000 4 KB
CPT2_AGGR4_MEM4 0x4C3E164000 0x4C3E165000 4 KB
CPT2_AGGR4_MEM5 0x4C3E165000 0x4C3E166000 4 KB
CPT2_AGGR4_MEM6 0x4C3E166000 0x4C3E167000 4 KB
CPT2_AGGR4_MEM7 0x4C3E167000 0x4C3E168000 4 KB
CPT2_AGGR4_MEM8 0x4C3E168000 0x4C3E169000 4 KB
CPT2_AGGR4_MEM9 0x4C3E169000 0x4C3E16A000 4 KB
CPT2_AGGR4_MEM10 0x4C3E16A000 0x4C3E16B000 4 KB
CPT2_AGGR4_MEM11 0x4C3E16B000 0x4C3E16C000 4 KB
CPT2_AGGR4_MEM12 0x4C3E16C000 0x4C3E16D000 4 KB
CPT2_AGGR4_MEM13 0x4C3E16D000 0x4C3E16E000 4 KB
CPT2_AGGR4_MEM14 0x4C3E16E000 0x4C3E16F000 4 KB
CPT2_AGGR4_MEM15 0x4C3E16F000 0x4C3E170000 4 KB
CPT2_AGGR4_MEM16 0x4C3E170000 0x4C3E171000 4 KB
CPT2_AGGR4_MEM17 0x4C3E171000 0x4C3E172000 4 KB
CPT2_AGGR4_MEM18 0x4C3E172000 0x4C3E173000 4 KB
CPT2_AGGR4_MEM19 0x4C3E173000 0x4C3E174000 4 KB
CPT2_AGGR4_MEM20 0x4C3E174000 0x4C3E175000 4 KB
CPT2_AGGR4_MEM21 0x4C3E175000 0x4C3E176000 4 KB
CPT2_AGGR4_MEM22 0x4C3E176000 0x4C3E177000 4 KB
CPT2_AGGR4_MEM23 0x4C3E177000 0x4C3E178000 4 KB
CPT2_AGGR4_MEM24 0x4C3E178000 0x4C3E179000 4 KB
CPT2_AGGR4_MEM25 0x4C3E179000 0x4C3E17A000 4 KB
CPT2_AGGR4_MEM26 0x4C3E17A000 0x4C3E17B000 4 KB
CPT2_AGGR4_MEM27 0x4C3E17B000 0x4C3E17C000 4 KB
CPT2_AGGR4_MEM28 0x4C3E17C000 0x4C3E17D000 4 KB
CPT2_AGGR4_MEM29 0x4C3E17D000 0x4C3E17E000 4 KB
CPT2_AGGR4_MEM30 0x4C3E17E000 0x4C3E17F000 4 KB
CPT2_AGGR4_MEM31 0x4C3E17F000 0x4C3E180000 4 KB
CPT2_AGGR1_MMR 0x4C3E180000 0x4C3E180100 256 B
CPT2_AGGR1_STP2ATB_CFG 0x4C3E180100 0x4C3E180200 256 B
CPT2_AGGR1_MEM0 0x4C3E1A0000 0x4C3E1A1000 4 KB
CPT2_AGGR1_MEM1 0x4C3E1A1000 0x4C3E1A2000 4 KB
CPT2_AGGR1_MEM2 0x4C3E1A2000 0x4C3E1A3000 4 KB
CPT2_AGGR1_MEM3 0x4C3E1A3000 0x4C3E1A4000 4 KB
CPT2_AGGR1_MEM4 0x4C3E1A4000 0x4C3E1A5000 4 KB
CPT2_AGGR1_MEM5 0x4C3E1A5000 0x4C3E1A6000 4 KB
CPT2_AGGR1_MEM6 0x4C3E1A6000 0x4C3E1A7000 4 KB
CPT2_AGGR1_MEM7 0x4C3E1A7000 0x4C3E1A8000 4 KB
CPT2_AGGR1_MEM8 0x4C3E1A8000 0x4C3E1A9000 4 KB
CPT2_AGGR1_MEM9 0x4C3E1A9000 0x4C3E1AA000 4 KB
CPT2_AGGR1_MEM10 0x4C3E1AA000 0x4C3E1AB000 4 KB
CPT2_AGGR1_MEM11 0x4C3E1AB000 0x4C3E1AC000 4 KB
CPT2_AGGR1_MEM12 0x4C3E1AC000 0x4C3E1AD000 4 KB
CPT2_AGGR1_MEM13 0x4C3E1AD000 0x4C3E1AE000 4 KB
CPT2_AGGR1_MEM14 0x4C3E1AE000 0x4C3E1AF000 4 KB
CPT2_AGGR1_MEM15 0x4C3E1AF000 0x4C3E1B0000 4 KB
CPT2_AGGR1_MEM16 0x4C3E1B0000 0x4C3E1B1000 4 KB
CPT2_AGGR1_MEM17 0x4C3E1B1000 0x4C3E1B2000 4 KB
CPT2_AGGR1_MEM18 0x4C3E1B2000 0x4C3E1B3000 4 KB
CPT2_AGGR1_MEM19 0x4C3E1B3000 0x4C3E1B4000 4 KB
CPT2_AGGR1_MEM20 0x4C3E1B4000 0x4C3E1B5000 4 KB
CPT2_AGGR1_MEM21 0x4C3E1B5000 0x4C3E1B6000 4 KB
CPT2_AGGR1_MEM22 0x4C3E1B6000 0x4C3E1B7000 4 KB
CPT2_AGGR1_MEM23 0x4C3E1B7000 0x4C3E1B8000 4 KB
CPT2_AGGR1_MEM24 0x4C3E1B8000 0x4C3E1B9000 4 KB
CPT2_AGGR1_MEM25 0x4C3E1B9000 0x4C3E1BA000 4 KB
CPT2_AGGR1_MEM26 0x4C3E1BA000 0x4C3E1BB000 4 KB
CPT2_AGGR1_MEM27 0x4C3E1BB000 0x4C3E1BC000 4 KB
CPT2_AGGR1_MEM28 0x4C3E1BC000 0x4C3E1BD000 4 KB
CPT2_AGGR1_MEM29 0x4C3E1BD000 0x4C3E1BE000 4 KB
CPT2_AGGR1_MEM30 0x4C3E1BE000 0x4C3E1BF000 4 KB
CPT2_AGGR1_MEM31 0x4C3E1BF000 0x4C3E1C0000 4 KB
CPT2_AGGR3_MMR 0x4C3E1C0000 0x4C3E1C0100 256 B
CPT2_AGGR3_STP2ATB_CFG 0x4C3E1C0100 0x4C3E1C0200 256 B
CPT2_AGGR3_MEM0 0x4C3E1E0000 0x4C3E1E1000 4 KB
CPT2_AGGR3_MEM1 0x4C3E1E1000 0x4C3E1E2000 4 KB
CPT2_AGGR3_MEM2 0x4C3E1E2000 0x4C3E1E3000 4 KB
CPT2_AGGR3_MEM3 0x4C3E1E3000 0x4C3E1E4000 4 KB
CPT2_AGGR3_MEM4 0x4C3E1E4000 0x4C3E1E5000 4 KB
CPT2_AGGR3_MEM5 0x4C3E1E5000 0x4C3E1E6000 4 KB
CPT2_AGGR3_MEM6 0x4C3E1E6000 0x4C3E1E7000 4 KB
CPT2_AGGR3_MEM7 0x4C3E1E7000 0x4C3E1E8000 4 KB
CPT2_AGGR3_MEM8 0x4C3E1E8000 0x4C3E1E9000 4 KB
CPT2_AGGR3_MEM9 0x4C3E1E9000 0x4C3E1EA000 4 KB
CPT2_AGGR3_MEM10 0x4C3E1EA000 0x4C3E1EB000 4 KB
CPT2_AGGR3_MEM11 0x4C3E1EB000 0x4C3E1EC000 4 KB
CPT2_AGGR3_MEM12 0x4C3E1EC000 0x4C3E1ED000 4 KB
CPT2_AGGR3_MEM13 0x4C3E1ED000 0x4C3E1EE000 4 KB
CPT2_AGGR3_MEM14 0x4C3E1EE000 0x4C3E1EF000 4 KB
CPT2_AGGR3_MEM15 0x4C3E1EF000 0x4C3E1F0000 4 KB
CPT2_AGGR3_MEM16 0x4C3E1F0000 0x4C3E1F1000 4 KB
CPT2_AGGR3_MEM17 0x4C3E1F1000 0x4C3E1F2000 4 KB
CPT2_AGGR3_MEM18 0x4C3E1F2000 0x4C3E1F3000 4 KB
CPT2_AGGR3_MEM19 0x4C3E1F3000 0x4C3E1F4000 4 KB
CPT2_AGGR3_MEM20 0x4C3E1F4000 0x4C3E1F5000 4 KB
CPT2_AGGR3_MEM21 0x4C3E1F5000 0x4C3E1F6000 4 KB
CPT2_AGGR3_MEM22 0x4C3E1F6000 0x4C3E1F7000 4 KB
CPT2_AGGR3_MEM23 0x4C3E1F7000 0x4C3E1F8000 4 KB
CPT2_AGGR3_MEM24 0x4C3E1F8000 0x4C3E1F9000 4 KB
CPT2_AGGR3_MEM25 0x4C3E1F9000 0x4C3E1FA000 4 KB
CPT2_AGGR3_MEM26 0x4C3E1FA000 0x4C3E1FB000 4 KB
CPT2_AGGR3_MEM27 0x4C3E1FB000 0x4C3E1FC000 4 KB
CPT2_AGGR3_MEM28 0x4C3E1FC000 0x4C3E1FD000 4 KB
CPT2_AGGR3_MEM29 0x4C3E1FD000 0x4C3E1FE000 4 KB
CPT2_AGGR3_MEM30 0x4C3E1FE000 0x4C3E1FF000 4 KB
CPT2_AGGR3_MEM31 0x4C3E1FF000 0x4C3E200000 4 KB
CPT2_AGGR2_MMR 0x4C3E200000 0x4C3E200100 256 B
CPT2_AGGR2_STP2ATB_CFG 0x4C3E200100 0x4C3E200200 256 B
CPT2_AGGR2_MEM0 0x4C3E220000 0x4C3E221000 4 KB
CPT2_AGGR2_MEM1 0x4C3E221000 0x4C3E222000 4 KB
CPT2_AGGR2_MEM2 0x4C3E222000 0x4C3E223000 4 KB
CPT2_AGGR2_MEM3 0x4C3E223000 0x4C3E224000 4 KB
CPT2_AGGR2_MEM4 0x4C3E224000 0x4C3E225000 4 KB
CPT2_AGGR2_MEM5 0x4C3E225000 0x4C3E226000 4 KB
CPT2_AGGR2_MEM6 0x4C3E226000 0x4C3E227000 4 KB
CPT2_AGGR2_MEM7 0x4C3E227000 0x4C3E228000 4 KB
CPT2_AGGR2_MEM8 0x4C3E228000 0x4C3E229000 4 KB
CPT2_AGGR2_MEM9 0x4C3E229000 0x4C3E22A000 4 KB
CPT2_AGGR2_MEM10 0x4C3E22A000 0x4C3E22B000 4 KB
CPT2_AGGR2_MEM11 0x4C3E22B000 0x4C3E22C000 4 KB
CPT2_AGGR2_MEM12 0x4C3E22C000 0x4C3E22D000 4 KB
CPT2_AGGR2_MEM13 0x4C3E22D000 0x4C3E22E000 4 KB
CPT2_AGGR2_MEM14 0x4C3E22E000 0x4C3E22F000 4 KB
CPT2_AGGR2_MEM15 0x4C3E22F000 0x4C3E230000 4 KB
CPT2_AGGR2_MEM16 0x4C3E230000 0x4C3E231000 4 KB
CPT2_AGGR2_MEM17 0x4C3E231000 0x4C3E232000 4 KB
CPT2_AGGR2_MEM18 0x4C3E232000 0x4C3E233000 4 KB
CPT2_AGGR2_MEM19 0x4C3E233000 0x4C3E234000 4 KB
CPT2_AGGR2_MEM20 0x4C3E234000 0x4C3E235000 4 KB
CPT2_AGGR2_MEM21 0x4C3E235000 0x4C3E236000 4 KB
CPT2_AGGR2_MEM22 0x4C3E236000 0x4C3E237000 4 KB
CPT2_AGGR2_MEM23 0x4C3E237000 0x4C3E238000 4 KB
CPT2_AGGR2_MEM24 0x4C3E238000 0x4C3E239000 4 KB
CPT2_AGGR2_MEM25 0x4C3E239000 0x4C3E23A000 4 KB
CPT2_AGGR2_MEM26 0x4C3E23A000 0x4C3E23B000 4 KB
CPT2_AGGR2_MEM27 0x4C3E23B000 0x4C3E23C000 4 KB
CPT2_AGGR2_MEM28 0x4C3E23C000 0x4C3E23D000 4 KB
CPT2_AGGR2_MEM29 0x4C3E23D000 0x4C3E23E000 4 KB
CPT2_AGGR2_MEM30 0x4C3E23E000 0x4C3E23F000 4 KB
CPT2_AGGR2_MEM31 0x4C3E23F000 0x4C3E240000 4 KB
CPT2_AGGR5_MMR 0x4C3E240000 0x4C3E240100 256 B
CPT2_AGGR5_STP2ATB_CFG 0x4C3E240100 0x4C3E240200 256 B
CPT2_AGGR5_MEM0 0x4C3E260000 0x4C3E261000 4 KB
CPT2_AGGR5_MEM1 0x4C3E261000 0x4C3E262000 4 KB
CPT2_AGGR5_MEM2 0x4C3E262000 0x4C3E263000 4 KB
CPT2_AGGR5_MEM3 0x4C3E263000 0x4C3E264000 4 KB
CPT2_AGGR5_MEM4 0x4C3E264000 0x4C3E265000 4 KB
CPT2_AGGR5_MEM5 0x4C3E265000 0x4C3E266000 4 KB
CPT2_AGGR5_MEM6 0x4C3E266000 0x4C3E267000 4 KB
CPT2_AGGR5_MEM7 0x4C3E267000 0x4C3E268000 4 KB
CPT2_AGGR5_MEM8 0x4C3E268000 0x4C3E269000 4 KB
CPT2_AGGR5_MEM9 0x4C3E269000 0x4C3E26A000 4 KB
CPT2_AGGR5_MEM10 0x4C3E26A000 0x4C3E26B000 4 KB
CPT2_AGGR5_MEM11 0x4C3E26B000 0x4C3E26C000 4 KB
CPT2_AGGR5_MEM12 0x4C3E26C000 0x4C3E26D000 4 KB
CPT2_AGGR5_MEM13 0x4C3E26D000 0x4C3E26E000 4 KB
CPT2_AGGR5_MEM14 0x4C3E26E000 0x4C3E26F000 4 KB
CPT2_AGGR5_MEM15 0x4C3E26F000 0x4C3E270000 4 KB
CPT2_AGGR5_MEM16 0x4C3E270000 0x4C3E271000 4 KB
CPT2_AGGR5_MEM17 0x4C3E271000 0x4C3E272000 4 KB
CPT2_AGGR5_MEM18 0x4C3E272000 0x4C3E273000 4 KB
CPT2_AGGR5_MEM19 0x4C3E273000 0x4C3E274000 4 KB
CPT2_AGGR5_MEM20 0x4C3E274000 0x4C3E275000 4 KB
CPT2_AGGR5_MEM21 0x4C3E275000 0x4C3E276000 4 KB
CPT2_AGGR5_MEM22 0x4C3E276000 0x4C3E277000 4 KB
CPT2_AGGR5_MEM23 0x4C3E277000 0x4C3E278000 4 KB
CPT2_AGGR5_MEM24 0x4C3E278000 0x4C3E279000 4 KB
CPT2_AGGR5_MEM25 0x4C3E279000 0x4C3E27A000 4 KB
CPT2_AGGR5_MEM26 0x4C3E27A000 0x4C3E27B000 4 KB
CPT2_AGGR5_MEM27 0x4C3E27B000 0x4C3E27C000 4 KB
CPT2_AGGR5_MEM28 0x4C3E27C000 0x4C3E27D000 4 KB
CPT2_AGGR5_MEM29 0x4C3E27D000 0x4C3E27E000 4 KB
CPT2_AGGR5_MEM30 0x4C3E27E000 0x4C3E27F000 4 KB
CPT2_AGGR5_MEM31 0x4C3E27F000 0x4C3E280000 4 KB
DEBUGSS_WRAP0_ROM_TABLE_0_1 0x4C40000000 0x4C40001000 4 KB
DEBUGSS_WRAP0_RESV0_1 0x4C40001000 0x4C40002000 4 KB
DEBUGSS_WRAP0_CFGAP1 0x4C40002000 0x4C40002100 256 B
DEBUGSS_WRAP0_APBAP1 0x4C40002100 0x4C40002200 256 B
DEBUGSS_WRAP0_AXIAP1 0x4C40002200 0x4C40002300 256 B
DEBUGSS_WRAP0_PWRAP1 0x4C40002300 0x4C40002400 256 B
DEBUGSS_WRAP0_PVIEW1 0x4C40002400 0x4C40002500 256 B
DEBUGSS_WRAP0_JTAGAP1 0x4C40002500 0x4C40002600 256 B
DEBUGSS_WRAP0_SECAP1 0x4C40002600 0x4C40002700 256 B
DEBUGSS_WRAP0_CORTEX0_CFG1 0x4C40002700 0x4C40002800 256 B
DEBUGSS_WRAP0_CORTEX1_CFG1 0x4C40002800 0x4C40002900 256 B
DEBUGSS_WRAP0_CORTEX2_CFG1 0x4C40002900 0x4C40002A00 256 B
DEBUGSS_WRAP0_CORTEX3_CFG1 0x4C40002A00 0x4C40002B00 256 B
DEBUGSS_WRAP0_CORTEX4_CFG1 0x4C40002B00 0x4C40002C00 256 B
DEBUGSS_WRAP0_CORTEX5_CFG1 0x4C40002C00 0x4C40002D00 256 B
DEBUGSS_WRAP0_CORTEX6_CFG1 0x4C40002D00 0x4C40002E00 256 B
DEBUGSS_WRAP0_CORTEX7_CFG1 0x4C40002E00 0x4C40002F00 256 B
DEBUGSS_WRAP0_CORTEX8_CFG1 0x4C40002F00 0x4C40003000 256 B
DEBUGSS_WRAP0_RESV1_1 0x4C40003000 0x4C40004000 4 KB
DEBUGSS_WRAP0_RESV2_1 0x4C40004000 0x4C42004000 32 MB
DEBUGSS_WRAP0_ROM_TABLE_1_1 0x4C60000000 0x4C60001000 4 KB
DEBUGSS_WRAP0_CSCTI1 0x4C60001000 0x4C60002000 4 KB
DEBUGSS_WRAP0_DRM1 0x4C60002000 0x4C60003000 4 KB
DEBUGSS_WRAP0_RESV3_1 0x4C60003000 0x4C60004000 4 KB
DEBUGSS_WRAP0_CSTPIU1 0x4C60004000 0x4C60005000 4 KB
DEBUGSS_WRAP0_CTF1 0x4C60005000 0x4C60006000 4 KB
DEBUGSS_WRAP0_RESV4_1 0x4C60006000 0x4C61006000 16 MB
DEBUGSS_WRAP0_EXT_APB1 0x4C70000000 0x4C80000000 256 MB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_MSMC_PBIST0_CFG_MSMC_PBIST0 0x4D10000000 0x4D10010000 64 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_PBIST0_0 0x4D10010000 0x4D10010400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_PBIST0_1 0x4D10010400 0x4D10010800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_PBIST1_0 0x4D10020000 0x4D10020400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_PBIST1_1 0x4D10020400 0x4D10020800 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW4_CFG_DSP_PBIST4 0x4D10050000 0x4D10050400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW5_CFG_DSP_PBIST5 0x4D10060000 0x4D10060400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW6_CFG_DSP_PBIST6 0x4D10070000 0x4D10070400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW7_CFG_DSP_PBIST7 0x4D10080000 0x4D10080400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW4_CFG_MSMC1_PBIST4 0x4D10090000 0x4D100A0000 64 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW5_CFG_MSMC1_PBIST5 0x4D100A0000 0x4D100B0000 64 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW6_CFG_MSMC1_PBIST6 0x4D100B0000 0x4D100C0000 64 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW7_CFG_MSMC1_PBIST7 0x4D100C0000 0x4D100D0000 64 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC_ECC_AGGR0_CFG_MSMC_ECC0 0x4D20000000 0x4D20000400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC_ECC_AGGR1_CFG_MSMC_ECC1 0x4D20000400 0x4D20000800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC_DDR_0_ECC_AGGR_CFG_MSMC_ECC2 0x4D20000800 0x4D20000C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC_DDR_1_ECC_AGGR_CFG_MSMC_ECC3 0x4D20000C00 0x4D20001000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC_DDR_2_ECC_AGGR_CFG_MSMC_ECC4 0x4D20001000 0x4D20001400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC_DDR_3_ECC_AGGR_CFG_MSMC_ECC5 0x4D20001400 0x4D20001800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC2_ECC_AGGR0_CFG_MSMC_ECC0 0x4D20002000 0x4D20002400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_MSMC2_ECC_AGGR1_CFG_MSMC_ECC1 0x4D20002400 0x4D20002800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_ECC_COREPAC 0x4D20010000 0x4D20010400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_ECC_CORE0 0x4D20010400 0x4D20010800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_ECC_CORE1 0x4D20010800 0x4D20010C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_ECC_CORE2 0x4D20010C00 0x4D20011000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG0_CFG_ARM_ECC_CORE3 0x4D20011000 0x4D20011400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_ECC_COREPAC 0x4D20020000 0x4D20020400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_ECC_CORE0 0x4D20020400 0x4D20020800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_ECC_CORE1 0x4D20020800 0x4D20020C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_ECC_CORE2 0x4D20020C00 0x4D20021000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_CFG1_CFG_ARM_ECC_CORE3 0x4D20021000 0x4D20021400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW4_CFG_DSP_ECCAGGR4 0x4D20050000 0x4D20050400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW4_CFG_MSMC1_ECC0 0x4D20051400 0x4D20051800 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW4_CFG_MSMC1_ECC1 0x4D20051800 0x4D20051C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW5_CFG_DSP_ECCAGGR5 0x4D20060000 0x4D20060400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW5_CFG_MSMC1_ECC0 0x4D20061400 0x4D20061800 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW5_CFG_MSMC1_ECC1 0x4D20061800 0x4D20061C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW6_CFG_DSP_ECCAGGR6 0x4D20070000 0x4D20070400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW6_CFG_MSMC1_ECC0 0x4D20071400 0x4D20071800 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW6_CFG_MSMC1_ECC1 0x4D20071800 0x4D20071C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW7_CFG_DSP_ECCAGGR7 0x4D20080000 0x4D20080400 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW7_CFG_MSMC1_ECC0 0x4D20081400 0x4D20081800 1 KB
COMPUTE_CLUSTERHP0_VBUSP4_CFG_AW7_CFG_MSMC1_ECC1 0x4D20081800 0x4D20081C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS0_ECC_AGGR_CTL 0x4D200B0000 0x4D200B0400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS0_ECC_AGGR_VBUS 0x4D200B0400 0x4D200B0800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS0_ECC_AGGR_CFG 0x4D200B0800 0x4D200B0C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS1_ECC_AGGR_CTL 0x4D200B0C00 0x4D200B1000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS1_ECC_AGGR_VBUS 0x4D200B1000 0x4D200B1400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS1_ECC_AGGR_CFG 0x4D200B1400 0x4D200B1800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS2_ECC_AGGR_CTL 0x4D200B1800 0x4D200B1C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS2_ECC_AGGR_VBUS 0x4D200B1C00 0x4D200B2000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS2_ECC_AGGR_CFG 0x4D200B2000 0x4D200B2400 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS3_ECC_AGGR_CTL 0x4D200B2400 0x4D200B2800 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS3_ECC_AGGR_VBUS 0x4D200B2800 0x4D200B2C00 1 KB
COMPUTE_CLUSTERHP0_VBUSP_DDRSS3_ECC_AGGR_CFG 0x4D200B2C00 0x4D200B3000 1 KB
COMPUTE_CLUSTERHP0_VBUSP_GICSS_ECC_AGGR_GIC_ECC_AGGR 0x4D200C0000 0x4D200C0400 1 KB
COMPUTE_CLUSTERHP0_GICSS_VBUSM_GASKET_CFG_GICSS_VBUSM_GASKET_CFG 0x4D200C0400 0x4D200C0800 1 KB
COMPUTE_CLUSTERHP0_CC 0x4D21000000 0x4D21010000 64 KB
R5FSS0_CORE0_ICACHE 0x4E00000000 0x4E00800000 8 MB
R5FSS0_CORE0_DCACHE 0x4E00800000 0x4E01000000 8 MB
R5FSS0_CORE1_ICACHE 0x4E01000000 0x4E01800000 8 MB
R5FSS0_CORE1_DCACHE 0x4E01800000 0x4E02000000 8 MB
R5FSS1_CORE0_ICACHE 0x4E10000000 0x4E10800000 8 MB
R5FSS1_CORE0_DCACHE 0x4E10800000 0x4E11000000 8 MB
R5FSS1_CORE1_ICACHE 0x4E11000000 0x4E11800000 8 MB
R5FSS1_CORE1_DCACHE 0x4E11800000 0x4E12000000 8 MB
AEP_GPU_BXS464_WRAP0_CORE_MMRS 0x4E20000000 0x4E20080000 512 KB
R5FSS2_CORE0_ICACHE 0x4E30000000 0x4E30800000 8 MB
R5FSS2_CORE0_DCACHE 0x4E30800000 0x4E31000000 8 MB
R5FSS2_CORE1_ICACHE 0x4E31000000 0x4E31800000 8 MB
R5FSS2_CORE1_DCACHE 0x4E31800000 0x4E32000000 8 MB
VPAC0_VPAC_TOP_PAC_BASE_MEM_SLV_CBASS_STRIPE_MSRAM_SLV 0x4F00000000 0x4F00080000 512 KB
VPAC1_VPAC_TOP_PAC_BASE_MEM_SLV_CBASS_STRIPE_MSRAM_SLV 0x4F00400000 0x4F00480000 512 KB
DMPAC0_DMPAC_TOP_DOF_INFRA_DMPAC_BASE_MEM_SLV_CBASS_STRIPE_MSRAM_SLV 0x4F01000000 0x4F01080000 512 KB
MSRAM_512K0_RAM 0x4F02000000 0x4F02080000 512 KB
MSRAM_512K1_RAM 0x4F02080000 0x4F02100000 512 KB
MSRAM_512K2_RAM 0x4F02100000 0x4F02180000 512 KB
VUSR_DUAL0_VUSR_PORTAL 0x5800000000 0x5900000000 4 GB