SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 6-80 lists the interupts generated by the MSC module.
Interrupt | Type | Description |
---|---|---|
VPAC_MSC_LSE_FR_DONE_EVT_0 | Pulse | Frame Processing complete for all filters in the processing thread 0. |
VPAC_MSC_LSE_FR_DONE_EVT_1 | Pulse | Frame Processing complete for all filters in the processing thread 1. |
VPAC_MSC_LSE_SL2_RD_ERR | Pulse | Set whenever there is an error response on VBUSM read command request for any input channel |
VPAC_MSC_LSE_SL2_WR_ERR | Pulse | Set whenever there is an error response on VBUSM write command request for any output channel |
All interrupts are single pulse event signals that are mapped to the VPAC level interrupt aggregation logic. The MSC has no mask/set/clear registers for these events. For more information see Section 6.7.2, VPAC Subsystem.