SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Unlike most of the device modules whose associated firewalls reside on system interconnect (CBASS) level the DRU has its own embedded firewalls. They are the following:
The region based firewall should be configured to cover the range from 0x6D00 4000 to 0x6D0C FFFF. This allows for a single master to control the memory attribute channels and channel ownership. If the region based firewall is configured to overlap the channelized firewall then both firewall checks have to pass for the register update to occur. If the firewall check fails the DRU returns protection error status to the requestor.
Protection error takes precedence over address error. If the address falls into the firewall protected range then a protection error is returned.
Each SoC DRU (DRU0 and DRU1) has both the region based and channelized firewall.
The DRU region based and channelized firewalls are same as the other device firewalls. For more information about their functionality, see Interconnect Firewalls in System Interconnect. The DRU firewall associated registers are described in the DRU Registers sections.