SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Table 5-34 summarizes the full connectivity of input clocks, module clocks, and PLLs.
Module Name | Module Port Name | Clock Source | Divider | Control Register | Mux Value | Default Mux Value | Typical Frequency |
---|---|---|---|---|---|---|---|
WKUP Domain | |||||||
WKUP_DDPA_0 | DDPA_CLK | MCU_SYSCLK0 | 6 | ||||
WKUP_ESM_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
WKUP_GPIO_0 | VBUS_CLK | MCU_SYSCLK0 | 6 | WKUP_GPIO_CLKSEL[1:0] | 0 | 0 | 167 MHz |
WKUP_GPIO_0 | VBUS_CLK | MCU_SYSCLK0 | 6 | WKUP_GPIO_CLKSEL[1:0] | 1 | 0 | 167 MHz |
WKUP_GPIO_0 | VBUS_CLK | CLK_32K | 6 | WKUP_GPIO_CLKSEL[1:0] | 2 | 0 | 32 KHz |
WKUP_GPIO_0 | VBUS_CLK | CLK_12M_RC | 6 | WKUP_GPIO_CLKSEL[1:0] | 3 | 0 | 12 MHz |
WKUP_GPIO_1 | VBUS_CLK | MCU_SYSCLK0 | 6 | WKUP_GPIO_CLKSEL[1:0] | 0 | 0 | 167 MHz |
WKUP_GPIO_1 | VBUS_CLK | MCU_SYSCLK0 | 6 | WKUP_GPIO_CLKSEL[1:0] | 1 | 0 | 167 MHz |
WKUP_GPIO_1 | VBUS_CLK | CLK_32K | 6 | WKUP_GPIO_CLKSEL[1:0] | 2 | 0 | 32 KHz |
WKUP_GPIO_1 | VBUS_CLK | CLK_12M_RC | 6 | WKUP_GPIO_CLKSEL[1:0] | 3 | 0 | 12 MHz |
WKUP_I2C_0 | OCP_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
WKUP_I2C_0 | SYS_CLK | MCU_PLL_1.HSDIVOUT3_CLK | 1 | WKUP_PER_CLKSEL[0:0] | 0 | 0 | |
WKUP_I2C_0 | SYS_CLK | HFOSC_0 | 1 | WKUP_PER_CLKSEL[0:0] | 1 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
WKUP_SMS_0 | EXT_CLK | MCU_EXT_REFCLK0 | 1 | ||||
WKUP_SMS_0 | FUNC_32K_RC_CLK | CLK_32K | 1 | 32 KHz | |||
WKUP_SMS_0 | FUNC_32K_RT_CLK | LFOSC | 1 | 32 KHz | |||
WKUP_SMS_0 | FUNC_MOSC_CLK | HFOSC_0 | 1 | [19.2, 20, 24, 25, 26, 27] MHz | |||
WKUP_SMS_0 | VBUS_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_SMS_M4F_0 | DAP_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_SMS_M4F_1 | DAP_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_SMS_RTI_0 | ICLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_SMS_RTI_1 | ICLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_UART_0 | FCLK | WKUP_USART_CLKSEL.OUT0 | 1 | WKUP_PER_CLKSEL[0:0] | 0 | 0 | |
WKUP_UART_0 | FCLK | HFOSC_0 | 1 | WKUP_PER_CLKSEL[0:0] | 1 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
WKUP_UART_0 | VBUS_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
WKUP_VTM_0 | FIX_REF_CLK | HFOSC_0 | 1 | [19.2, 20, 24, 25, 26, 27] MHz | |||
WKUP_VTM_0 | FIX_REF2_CLK | CLK_12M_RC | 1 | 12 MHz | |||
WKUP_VTM_0 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
WKUP_MMR_CTRL_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
WKUP_PLLCTRL_0 | PLL_CLKOUT_CLK | MCU_PLL_0.HSDIVOUT0_CLK | 1 | ||||
WKUP_PLLCTRL_0 | PLL_REFCLK_CLK | HFOSC_0 | 1 | MCU_PLL_CLKSEL[8:8] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
WKUP_PLLCTRL_0 | PLL_REFCLK_CLK | CLK_12M_RC | 1 | MCU_PLL_CLKSEL[8:8] | 1 | 0 | 12 MHz |
MCU_PBIST_0 | CLK1_CLK | MCU_SYSCLK0 | 2 | 500 MHz | |||
MCU_PBIST_0 | CLK2_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_PBIST_0 | CLK3_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_PBIST_0 | CLK4_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_0 | CLK5_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_0 | CLK6_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_0 | CLK7_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_0 | CLK8_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_1 | CLK1_CLK | MCU_SYSCLK0 | 2 | 500 MHz | |||
MCU_PBIST_1 | CLK2_CLK | MCU_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MCU_PBIST_1 | CLK3_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_PBIST_1 | CLK4_CLK | MCU_PLL_2.HSDIVOUT4_CLK | 2 | ||||
MCU_PBIST_1 | CLK5_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_PBIST_1 | CLK6_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_1 | CLK7_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_1 | CLK8_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
MCU_PBIST_R5FSS_0 | CLK8_CLK | MCU_SYSCLK0 | 12 | 83 MHz | |||
WKUP_INTROUTER_GPIOMUX_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
WKUP_SMS_M4F_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_SMS_M4F_ECC_AGGR_1 | ECC_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
WKUP_VTM_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU Domain | |||||||
MCU_ADC_0 | CLK | HFOSC_0 | 1 | MCU_ADC0_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_ADC_0 | CLK | MCU_PLL_1.HSDIVOUT1_CLK | 1 | MCU_ADC0_CLKSEL[1:0] | 1 | 0 | |
MCU_ADC_0 | CLK | MCU_PLL_0.HSDIVOUT1_CLK | 1 | MCU_ADC0_CLKSEL[1:0] | 2 | 0 | |
MCU_ADC_0 | CLK | MCU_EXT_REFCLK0 | 1 | MCU_ADC0_CLKSEL[1:0] | 3 | 0 | |
MCU_ADC_0 | SYS_CLK | MCU_SYSCLK0 | 2 | 500 MHz | |||
MCU_ADC_0 | VBUS_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_ADC_1 | CLK | HFOSC_0 | 1 | MCU_ADC1_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_ADC_1 | CLK | MCU_PLL_1.HSDIVOUT1_CLK | 1 | MCU_ADC1_CLKSEL[1:0] | 1 | 0 | |
MCU_ADC_1 | CLK | MCU_PLL_0.HSDIVOUT1_CLK | 1 | MCU_ADC1_CLKSEL[1:0] | 2 | 0 | |
MCU_ADC_1 | CLK | MCU_EXT_REFCLK0 | 1 | MCU_ADC1_CLKSEL[1:0] | 3 | 0 | |
MCU_ADC_1 | SYS_CLK | MCU_SYSCLK0 | 2 | 500 MHz | |||
MCU_ADC_1 | VBUS_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPSW2_0 | CPPI_ICLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPSW2_0 | CPTS_RCLK_DFT_LOCAL_CLK | MCU_SYSCLK0 | 2 | 500 MHz | |||
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | MCU_ENET_CLKSEL[11:8] | 0 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | MCU_ENET_CLKSEL[11:8] | 1 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MCU_CPTS0_RFT_CLK | 1 | MCU_ENET_CLKSEL[11:8] | 2 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | CPTS0_RFT_CLK | 1 | MCU_ENET_CLKSEL[11:8] | 3 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MCU_EXT_REFCLK0 | 1 | MCU_ENET_CLKSEL[11:8] | 4 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | EXT_REFCLK1 | 1 | MCU_ENET_CLKSEL[11:8] | 5 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 6 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 7 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 8 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 9 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 10 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 11 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 12 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | MCU_ENET_CLKSEL[11:8] | 13 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | MCU_ENET_CLKSEL[11:8] | 14 | 15 | |
MCU_CPSW2_0 | CPTS_RFT_CLK | POST_CLK_MUX.OUT0 | 1 | MCU_ENET_CLKSEL[11:8] | 15 | 15 | |
MCU_CPSW2_0 | GMII_RFT_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 2 | ||||
MCU_CPSW2_0 | GMII1_MR_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 10 | ||||
MCU_CPSW2_0 | GMII1_MT_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 10 | ||||
MCU_CPSW2_0 | RGMII_MHZ_250_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 1 | ||||
MCU_CPSW2_0 | RGMII_MHZ_5_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 50 | ||||
MCU_CPSW2_0 | RGMII_MHZ_50_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 5 | ||||
MCU_CPSW2_0 | RGMII1_RXC_I | MCU_RGMII1_RXC | 1 | ||||
MCU_CPSW2_0 | RMII_MHZ_50_CLK | MCU_RMII1_REF_CLK | 1 | ||||
MCU_DCC_0 | INPUT1_CLK | MCU_SYSCLK0 | 3 | DCC_CLKSRC1 | 0 | 0 | 333 MHz |
MCU_DCC_0 | INPUT1_CLK | MCU_PLL_1.HSDIVOUT0_CLK | 2 | DCC_CLKSRC1 | 1 | 0 | |
MCU_DCC_0 | INPUT1_CLK | MCU_PLL_1.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 | 2 | 0 | |
MCU_DCC_0 | INPUT1_CLK | MCU_PLL_1.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 3 | 0 | |
MCU_DCC_0 | INPUT1_CLK | MCU_PLL_1.HSDIVOUT3_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MCU_DCC_0 | INPUT1_CLK | MCU_PLL_1.HSDIVOUT4_CLK | 1 | DCC_CLKSRC1 | 5 | 0 | |
MCU_DCC_0 | INPUT1_CLK | CLK_32K | 1 | DCC_CLKSRC1 | 6 | 0 | 32 KHz |
MCU_DCC_0 | INPUT1_CLK | LFOSC | 1 | DCC_CLKSRC1 | 7 | 0 | 32 KHz |
MCU_DCC_0 | INPUT1_CLK | MCU_EXT_REFCLK0 | 1 | DCC_CLKSRC1 | 8 | 0 | |
MCU_DCC_0 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_DCC_0 | INPUT0_CLK | CLK_32K | 1 | DCC_CLKSRC0 | 1 | 0 | 32 KHz |
MCU_DCC_0 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MCU_DCC_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_2.HSDIVOUT0_CLK | 1 | DCC_CLKSRC1 | 0 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 2 | DCC_CLKSRC1 | 1 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_2.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 2 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_2.HSDIVOUT3_CLK | 1 | DCC_CLKSRC1 | 3 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_2.HSDIVOUT4_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_0.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 5 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_0.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 | 6 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MCU_OSPI0_LBCLKO | 1 | DCC_CLKSRC1 | 7 | 0 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 0 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 1 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MCU_CPTS0_RFT_CLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 2 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | CPTS0_RFT_CLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 3 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MCU_EXT_REFCLK0 | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 4 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | EXT_REFCLK1 | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 5 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 6 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 7 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 8 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 9 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 10 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 11 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 12 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 13 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 14 | 0 / 15 | |
MCU_DCC_1 | INPUT1_CLK | POST_CLK_MUX.OUT0 | 1 | DCC_CLKSRC1 / MCU_ENET_CLKSEL[11:8] | 8 / 15 | 0 / 15 | |
MCU_DCC_1 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_DCC_1 | INPUT0_CLK | LFOSC | 1 | DCC_CLKSRC0 | 1 | 0 | 32 KHz |
MCU_DCC_1 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MCU_DCC_1 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_DCC_2 | INPUT1_CLK | MCU_SYSCLK0 | 3 | DCC_CLKSRC1 | 0 | 0 | 333 MHz |
MCU_DCC_2 | INPUT1_CLK | MCU_RMII1_REF_CLK | 1 | DCC_CLKSRC1 | 1 | 0 | |
MCU_DCC_2 | INPUT1_CLK | MCU_RGMII1_RXC | 1 | DCC_CLKSRC1 | 2 | 0 | |
MCU_DCC_2 | INPUT1_CLK | HFOSC_1 | 1 | DCC_CLKSRC1 | 3 | 0 | [19.2, - 27] MHz |
MCU_DCC_2 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT5_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MCU_DCC_2 | INPUT1_CLK | MCU_OSPI1_LBCLKO | 1 | DCC_CLKSRC1 | 5 | 0 | |
MCU_DCC_2 | INPUT1_CLK | CLK_12M_RC | 1 | DCC_CLKSRC1 | 7 | 0 | 12 MHz |
MCU_DCC_2 | INPUT1_CLK | HFOSC_0 | 1 | DCC_CLKSRC1 | 8 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_DCC_2 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_DCC_2 | INPUT0_CLK | MCU_EXT_REFCLK0 | 1 | DCC_CLKSRC0 | 1 | 0 | |
MCU_DCC_2 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MCU_DCC_2 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_ESM_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_HYPERBUS_0 | HPB0_CLKX1 | MCU_PLL_2.HSDIVOUT4_CLK | 1 | ||||
MCU_HYPERBUS_0 | HPB0_CLKX1_INV | HPB_CLKX2_DIV2.OUT0 | 1 | ||||
MCU_HYPERBUS_0 | HPB0_CLKX2 | MCU_PLL_2.HSDIVOUT4_CLK | 1 | ||||
MCU_HYPERBUS_0 | HPB0_CLKX2_INV | MCU_PLL_2.HSDIVOUT4_CLK | 1 | ||||
MCU_HYPERBUS_0 | HPB0_ICLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_I2C_0 | OCP_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I2C_0 | SYS_CLK | MCU_PLL_1.HSDIVOUT3_CLK | 1 | ||||
MCU_I2C_1 | OCP_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I2C_1 | SYS_CLK | MCU_PLL_1.HSDIVOUT3_CLK | 1 | ||||
MCU_I3C_0 | PCLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I3C_0 | SCLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I3C_1 | PCLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I3C_1 | SCLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_MCAN_0 | FCLK | MCU_PLL_2.HSDIVOUT3_CLK | 1 | MCU_MCAN0_CLKSEL[1:0] | 0 | 0 | |
MCU_MCAN_0 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_MCAN0_CLKSEL[1:0] | 1 | 0 | |
MCU_MCAN_0 | FCLK | MCU_PLL_1.HSDIVOUT2_CLK | 1 | MCU_MCAN0_CLKSEL[1:0] | 2 | 0 | |
MCU_MCAN_0 | FCLK | HFOSC_0 | 1 | MCU_MCAN0_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_MCAN_0 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_MCAN_1 | FCLK | MCU_PLL_2.HSDIVOUT3_CLK | 1 | MCU_MCAN1_CLKSEL[1:0] | 0 | 0 | |
MCU_MCAN_1 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_MCAN1_CLKSEL[1:0] | 1 | 0 | |
MCU_MCAN_1 | FCLK | MCU_PLL_1.HSDIVOUT2_CLK | 1 | MCU_MCAN1_CLKSEL[1:0] | 2 | 0 | |
MCU_MCAN_1 | FCLK | HFOSC_0 | 1 | MCU_MCAN1_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_MCAN_1 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_OSPI_0 | DFT_LOCAL_DQS_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_0 | DFT_LOCAL_RCLK_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_0 | HCLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_0 | LOOPBACK | MCU_OSPI_0.OSPI_OCLK_CLK | 1 | MCU_OSPI0_CLKSEL[4:4] | 1 | 0 | |
MCU_OSPI_0 | PCLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_0 | RCLK | MCU_PLL_1.HSDIVOUT4_CLK | 1 | MCU_OSPI0_CLKSEL[0:0] | 0 | 0 | |
MCU_OSPI_0 | RCLK | MCU_PLL_2.HSDIVOUT4_CLK | 1 | MCU_OSPI0_CLKSEL[0:0] | 1 | 0 | |
MCU_OSPI_1 | DFT_LOCAL_DQS_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_1 | DFT_LOCAL_RCLK_CLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_1 | HCLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_1 | LOOPBACK | MCU_OSPI_1.OSPI_OCLK_CLK | 1 | MCU_OSPI1_CLKSEL[4:4] | 1 | 0 | |
MCU_OSPI_1 | PCLK | MCU_SYSCLK0 | 1 | 1000 MHz | |||
MCU_OSPI_1 | RCLK | MCU_PLL_1.HSDIVOUT4_CLK | 1 | MCU_OSPI1_CLKSEL[0:0] | 0 | 0 | |
MCU_OSPI_1 | RCLK | MCU_PLL_2.HSDIVOUT4_CLK | 1 | MCU_OSPI1_CLKSEL[0:0] | 1 | 0 | |
MCU_PLL_0 | FREF | HFOSC_0 | 1 | MCU_PLL_CLKSEL[8:8] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_PLL_0 | FREF | CLK_12M_RC | 1 | MCU_PLL_CLKSEL[8:8] | 1 | 0 | 12 MHz |
MCU_PLL_1 | FREF | HFOSC_0 | 1 | MCU_PLL_CLKSEL[8:8] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_PLL_1 | FREF | CLK_12M_RC | 1 | MCU_PLL_CLKSEL[8:8] | 1 | 0 | 12 MHz |
MCU_PLL_2 | FREF | HFOSC_0 | 1 | MCU_PLL_CLKSEL[8:8] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_PLL_2 | FREF | CLK_12M_RC | 1 | MCU_PLL_CLKSEL[8:8] | 1 | 0 | 12 MHz |
MCU_PSROM_0 | CLK_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_R5FSS_CORE_0 | FCLK | MCU_SYSCLK0 | 1 | MCU_R5_CORE0_CLKSEL[0:0] | 0 | 1000 MHz | |
MCU_R5FSS_CORE_0 | FCLK | MCU_SYSCLK0 | 3 | MCU_R5_CORE0_CLKSEL[0:0] | 1 | 0 | 1000 MHz |
MCU_R5FSS_CORE_1 | FCLK | MCU_SYSCLK0 | 1 | MCU_R5_CORE1_CLKSEL[0:0] | 0 | 1000 MHz | |
MCU_R5FSS_CORE_1 | FCLK | MCU_SYSCLK0 | 3 | MCU_R5_CORE1_CLKSEL[0:0] | 1 | 0 | 1000 MHz |
MCU_RTI_R5FSS_CORE_0 | FCLK | HFOSC_0 | 1 | MCU_RTI0_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_RTI_R5FSS_CORE_0 | FCLK | LFOSC | 1 | MCU_RTI0_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MCU_RTI_R5FSS_CORE_0 | FCLK | CLK_12M_RC | 1 | MCU_RTI0_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_RTI_R5FSS_CORE_0 | FCLK | CLK_32K | 1 | MCU_RTI0_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MCU_RTI_R5FSS_CORE_0 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_RTI_R5FSS_CORE_1 | FCLK | HFOSC_0 | 1 | MCU_RTI1_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_RTI_R5FSS_CORE_1 | FCLK | LFOSC | 1 | MCU_RTI1_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MCU_RTI_R5FSS_CORE_1 | FCLK | CLK_12M_RC | 1 | MCU_RTI1_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_RTI_R5FSS_CORE_1 | FCLK | CLK_32K | 1 | MCU_RTI1_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MCU_RTI_R5FSS_CORE_1 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_SPI_0 | FCLK | MCU_PLL_2.HSDIVOUT0_CLK | 1 | ||||
MCU_SPI_0 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_SPI_0 | IO_CLKSPII_CLK | MCU_SPI0_CLK | 1 | MCU_SPI0_CTRL[0:0] | 0 | 0 | |
MCU_SPI_0 | IO_CLKSPII_CLK | MCU_SPI_0.IO_CLKSPIO_CLK | 1 | MCU_SPI0_CTRL[0:0] | 1 | 0 | |
MCU_SPI_1 | FCLK | MCU_PLL_2.HSDIVOUT0_CLK | 1 | ||||
MCU_SPI_1 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_SPI_1 | IO_CLKSPII_CLK | MAIN_SPI_3.IO_CLKSPIO_CLK | 1 | MCU_SPI1_CTRL[0:0] | 0 | 0 | |
MCU_SPI_1 | IO_CLKSPII_CLK | MCU_SPI1_CLK_LPBK_MUX.OUT0 | 1 | MCU_SPI1_CTRL[0:0] | 1 | 0 | |
MCU_SPI_2 | FCLK | MCU_PLL_2.HSDIVOUT0_CLK | 1 | ||||
MCU_SPI_2 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_SPI_2 | IO_CLKSPII_CLK | MCU_SPI_2.IO_CLKSPIO_CLK | 1 | ||||
MCU_TIMER_0 | FCLK | HFOSC_0 | 1 | MCU_TIMER0_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_TIMER_0 | FCLK | POST_CLK_MUX.OUT0 | 1 | MCU_TIMER0_CLKSEL[2:0] | 1 | 0 | |
MCU_TIMER_0 | FCLK | CLK_12M_RC | 1 | MCU_TIMER0_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_TIMER_0 | FCLK | MCU_PLL_2.HSDIVOUT2_CLK | 1 | MCU_TIMER0_CLKSEL[2:0] | 3 | 0 | |
MCU_TIMER_0 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_TIMER0_CLKSEL[2:0] | 4 | 0 | |
MCU_TIMER_0 | FCLK | LFOSC | 1 | MCU_TIMER0_CLKSEL[2:0] | 5 | 0 | 32 KHz |
MCU_TIMER_0 | FCLK | MCU_CPSW2_0.CPTS_GENF0 | 1 | MCU_TIMER0_CLKSEL[2:0] | 6 | 0 | |
MCU_TIMER_0 | FCLK | CLK_32K | 1 | MCU_TIMER0_CLKSEL[2:0] | 7 | 0 | 32 KHz |
MCU_TIMER_0 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_1 | FCLK | MCU_TIMER_CLKSEL.OUT1 | 1 | MCU_TIMER1_CTRL[8:8] | 0 | 0 | |
MCU_TIMER_1 | FCLK | MCU_TIMER_0.TIMER_PWM | 1 | MCU_TIMER1_CTRL[8:8] | 1 | 0 | |
MCU_TIMER_1 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_2 | FCLK | HFOSC_0 | 1 | MCU_TIMER2_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_TIMER_2 | FCLK | POST_CLK_MUX.OUT0 | 1 | MCU_TIMER2_CLKSEL[2:0] | 1 | 0 | |
MCU_TIMER_2 | FCLK | CLK_12M_RC | 1 | MCU_TIMER2_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_TIMER_2 | FCLK | MCU_PLL_2.HSDIVOUT2_CLK | 1 | MCU_TIMER2_CLKSEL[2:0] | 3 | 0 | |
MCU_TIMER_2 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_TIMER2_CLKSEL[2:0] | 4 | 0 | |
MCU_TIMER_2 | FCLK | LFOSC | 1 | MCU_TIMER2_CLKSEL[2:0] | 5 | 0 | 32 KHz |
MCU_TIMER_2 | FCLK | MCU_CPSW2_0.CPTS_GENF0 | 1 | MCU_TIMER2_CLKSEL[2:0] | 6 | 0 | |
MCU_TIMER_2 | FCLK | CLK_32K | 1 | MCU_TIMER2_CLKSEL[2:0] | 7 | 0 | 32 KHz |
MCU_TIMER_2 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_3 | FCLK | MCU_TIMER_CLKSEL.OUT3 | 1 | MCU_TIMER3_CTRL[8:8] | 0 | 0 | |
MCU_TIMER_3 | FCLK | MCU_TIMER_2.TIMER_PWM | 1 | MCU_TIMER3_CTRL[8:8] | 1 | 0 | |
MCU_TIMER_3 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_4 | FCLK | HFOSC_0 | 1 | MCU_TIMER4_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_TIMER_4 | FCLK | POST_CLK_MUX.OUT0 | 1 | MCU_TIMER4_CLKSEL[2:0] | 1 | 0 | |
MCU_TIMER_4 | FCLK | CLK_12M_RC | 1 | MCU_TIMER4_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_TIMER_4 | FCLK | MCU_PLL_2.HSDIVOUT2_CLK | 1 | MCU_TIMER4_CLKSEL[2:0] | 3 | 0 | |
MCU_TIMER_4 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_TIMER4_CLKSEL[2:0] | 4 | 0 | |
MCU_TIMER_4 | FCLK | LFOSC | 1 | MCU_TIMER4_CLKSEL[2:0] | 5 | 0 | 32 KHz |
MCU_TIMER_4 | FCLK | MCU_CPSW2_0.CPTS_GENF0 | 1 | MCU_TIMER4_CLKSEL[2:0] | 6 | 0 | |
MCU_TIMER_4 | FCLK | CLK_32K | 1 | MCU_TIMER4_CLKSEL[2:0] | 7 | 0 | 32 KHz |
MCU_TIMER_4 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_5 | FCLK | MCU_TIMER_CLKSEL.OUT5 | 1 | MCU_TIMER5_CTRL[8:8] | 0 | 0 | |
MCU_TIMER_5 | FCLK | MCU_TIMER_4.TIMER_PWM | 1 | MCU_TIMER5_CTRL[8:8] | 1 | 0 | |
MCU_TIMER_5 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_6 | FCLK | HFOSC_0 | 1 | MCU_TIMER6_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_TIMER_6 | FCLK | POST_CLK_MUX.OUT0 | 1 | MCU_TIMER6_CLKSEL[2:0] | 1 | 0 | |
MCU_TIMER_6 | FCLK | CLK_12M_RC | 1 | MCU_TIMER6_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_TIMER_6 | FCLK | MCU_PLL_2.HSDIVOUT2_CLK | 1 | MCU_TIMER6_CLKSEL[2:0] | 3 | 0 | |
MCU_TIMER_6 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_TIMER6_CLKSEL[2:0] | 4 | 0 | |
MCU_TIMER_6 | FCLK | LFOSC | 1 | MCU_TIMER6_CLKSEL[2:0] | 5 | 0 | 32 KHz |
MCU_TIMER_6 | FCLK | MCU_CPSW2_0.CPTS_GENF0 | 1 | MCU_TIMER6_CLKSEL[2:0] | 6 | 0 | |
MCU_TIMER_6 | FCLK | CLK_32K | 1 | MCU_TIMER6_CLKSEL[2:0] | 7 | 0 | 32 KHz |
MCU_TIMER_6 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_7 | FCLK | MCU_TIMER_CLKSEL.OUT7 | 1 | MCU_TIMER7_CTRL[8:8] | 0 | 0 | |
MCU_TIMER_7 | FCLK | MCU_TIMER_6.TIMER_PWM | 1 | MCU_TIMER7_CTRL[8:8] | 1 | 0 | |
MCU_TIMER_7 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_8 | FCLK | HFOSC_0 | 1 | MCU_TIMER8_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_TIMER_8 | FCLK | POST_CLK_MUX.OUT0 | 1 | MCU_TIMER8_CLKSEL[2:0] | 1 | 0 | |
MCU_TIMER_8 | FCLK | CLK_12M_RC | 1 | MCU_TIMER8_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MCU_TIMER_8 | FCLK | MCU_PLL_2.HSDIVOUT2_CLK | 1 | MCU_TIMER8_CLKSEL[2:0] | 3 | 0 | |
MCU_TIMER_8 | FCLK | MCU_EXT_REFCLK0 | 1 | MCU_TIMER8_CLKSEL[2:0] | 4 | 0 | |
MCU_TIMER_8 | FCLK | LFOSC | 1 | MCU_TIMER8_CLKSEL[2:0] | 5 | 0 | 32 KHz |
MCU_TIMER_8 | FCLK | MCU_CPSW2_0.CPTS_GENF0 | 1 | MCU_TIMER8_CLKSEL[2:0] | 6 | 0 | |
MCU_TIMER_8 | FCLK | CLK_32K | 1 | MCU_TIMER8_CLKSEL[2:0] | 7 | 0 | 32 KHz |
MCU_TIMER_8 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_TIMER_9 | FCLK | MCU_TIMER_CLKSEL.OUT9 | 1 | MCU_TIMER9_CTRL[8:8] | 0 | 0 | |
MCU_TIMER_9 | FCLK | MCU_TIMER_8.TIMER_PWM | 1 | MCU_TIMER9_CTRL[8:8] | 1 | 0 | |
MCU_TIMER_9 | ICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_EFUSE_0 | PLL_CTRL_CLK | MCU_SYSCLK0 | 24 | 42 MHz | |||
MCU_EFUSE_0 | WKUP_OSC0_CLK | HFOSC_0 | 1 | MCU_EFUSE_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MCU_EFUSE_0 | WKUP_OSC0_CLK | MCU_SYSCLK0 | 1 | MCU_EFUSE_CLKSEL[0:0] | 1 | 0 | 1000 MHz |
MCU_MMR_CTRL_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_MMR_PLL_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_MMR_SEC_0 | FICLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_1MBYTE_SRAM_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_ADC_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_ADC_ECC_AGGR_1 | ECC_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_AGGR_0 | CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_EXPORT_RESP_0 | AGGR_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_EXPORT_RESP_0 | PROBE_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_FSS_0_2 | AGGR_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_FSS_0_2 | PROBE_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_FSS_1_3 | AGGR_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_FSS_1_3 | PROBE_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_SRAM_RESP_0 | AGGR_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_CPT2_PROBE_SRAM_RESP_0 | PROBE_CLK | MCU_SYSCLK0 | 3 | 333 MHz | |||
MCU_I3C_P_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I3C_P_ECC_AGGR_1 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I3C_S_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_I3C_S_ECC_AGGR_1 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_MCANSS_ECC_AGGR_0 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MCU_MCANSS_ECC_AGGR_1 | ECC_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MAIN Domain | |||||||
A72SS_0 | ARM0_CLK_CLK | MAIN_PLL_8.HSDIVOUT0_CLK | 1 | ||||
A72SS_1 | ARM1_CLK_CLK | MAIN_PLL_9.HSDIVOUT0_CLK | 1 | ||||
C71SS_0 | C7X_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 1 | ||||
C71SS_1 | C7X_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 1 | ||||
C71SS_2 | C7X_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 1 | ||||
C71SS_3 | C7X_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 1 | ||||
MAIN_ATL_0 | ATL_CLK | MAIN_PLL_4.HSDIVOUT1_CLK | 1 | ATL_CLKSEL[3:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | ATL_CLKSEL[3:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_CLK | MAIN_PLL_0.HSDIVOUT7_CLK | 1 | ATL_CLKSEL[3:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_CLK | MCU_EXT_REFCLK0 | 1 | ATL_CLKSEL[3:0] | 5 | 0 | |
MAIN_ATL_0 | ATL_CLK | EXT_REFCLK1 | 1 | ATL_CLKSEL[3:0] | 6 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS0_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | AUDIO_EXT_REFCLK0 | 1 | ATL_AWS0_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS | AUDIO_EXT_REFCLK1 | 1 | ATL_AWS0_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS1_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | AUDIO_EXT_REFCLK0 | 1 | ATL_AWS1_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_1 | AUDIO_EXT_REFCLK1 | 1 | ATL_AWS1_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS2_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | AUDIO_EXT_REFCLK0 | 1 | ATL_AWS2_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_2 | AUDIO_EXT_REFCLK1 | 1 | ATL_AWS2_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_AWS3_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | AUDIO_EXT_REFCLK0 | 1 | ATL_AWS3_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_AWS_3 | AUDIO_EXT_REFCLK1 | 1 | ATL_AWS3_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_0.MCASP_AFSR_POUT | 1 | ATL_BWS0_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_1.MCASP_AFSR_POUT | 1 | ATL_BWS0_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_2.MCASP_AFSR_POUT | 1 | ATL_BWS0_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_3.MCASP_AFSR_POUT | 1 | ATL_BWS0_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_4.MCASP_AFSR_POUT | 1 | ATL_BWS0_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_BWS0_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_BWS0_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_BWS0_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_BWS0_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_BWS0_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | AUDIO_EXT_REFCLK0 | 1 | ATL_BWS0_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS | AUDIO_EXT_REFCLK1 | 1 | ATL_BWS0_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_0.MCASP_AFSR_POUT | 1 | ATL_BWS1_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_1.MCASP_AFSR_POUT | 1 | ATL_BWS1_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_2.MCASP_AFSR_POUT | 1 | ATL_BWS1_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_3.MCASP_AFSR_POUT | 1 | ATL_BWS1_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_4.MCASP_AFSR_POUT | 1 | ATL_BWS1_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_BWS1_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_BWS1_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_BWS1_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_BWS1_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_BWS1_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | AUDIO_EXT_REFCLK0 | 1 | ATL_BWS1_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_1 | AUDIO_EXT_REFCLK1 | 1 | ATL_BWS1_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_0.MCASP_AFSR_POUT | 1 | ATL_BWS2_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_1.MCASP_AFSR_POUT | 1 | ATL_BWS2_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_2.MCASP_AFSR_POUT | 1 | ATL_BWS2_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_3.MCASP_AFSR_POUT | 1 | ATL_BWS2_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_4.MCASP_AFSR_POUT | 1 | ATL_BWS2_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_BWS2_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_BWS2_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_BWS2_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_BWS2_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_BWS2_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | AUDIO_EXT_REFCLK0 | 1 | ATL_BWS2_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_2 | AUDIO_EXT_REFCLK1 | 1 | ATL_BWS2_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_0.MCASP_AFSR_POUT | 1 | ATL_BWS3_SEL[4:0] | 0 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_1.MCASP_AFSR_POUT | 1 | ATL_BWS3_SEL[4:0] | 1 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_2.MCASP_AFSR_POUT | 1 | ATL_BWS3_SEL[4:0] | 2 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_3.MCASP_AFSR_POUT | 1 | ATL_BWS3_SEL[4:0] | 3 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_4.MCASP_AFSR_POUT | 1 | ATL_BWS3_SEL[4:0] | 4 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_0.MCASP_AFSX_POUT | 1 | ATL_BWS3_SEL[4:0] | 12 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_1.MCASP_AFSX_POUT | 1 | ATL_BWS3_SEL[4:0] | 13 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_2.MCASP_AFSX_POUT | 1 | ATL_BWS3_SEL[4:0] | 14 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_3.MCASP_AFSX_POUT | 1 | ATL_BWS3_SEL[4:0] | 15 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | MAIN_MCASP_4.MCASP_AFSX_POUT | 1 | ATL_BWS3_SEL[4:0] | 16 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | AUDIO_EXT_REFCLK0 | 1 | ATL_BWS3_SEL[4:0] | 24 | 0 | |
MAIN_ATL_0 | ATL_IO_PORT_BWS_3 | AUDIO_EXT_REFCLK1 | 1 | ATL_BWS3_SEL[4:0] | 25 | 0 | |
MAIN_ATL_0 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPSW2_0 | CPPI_ICLK | MAIN_PLL_1.HSDIVOUT1_CLK | 1 | ||||
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | CPSW2_CLKSEL[3:0] | 0 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | CPSW2_CLKSEL[3:0] | 1 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MCU_CPTS0_RFT_CLK | 1 | CPSW2_CLKSEL[3:0] | 2 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | CPTS0_RFT_CLK | 1 | CPSW2_CLKSEL[3:0] | 3 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MCU_EXT_REFCLK0 | 1 | CPSW2_CLKSEL[3:0] | 4 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | EXT_REFCLK1 | 1 | CPSW2_CLKSEL[3:0] | 5 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 6 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 7 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 8 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 9 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 10 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 11 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 12 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | CPSW2_CLKSEL[3:0] | 13 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | CPSW2_CLKSEL[3:0] | 14 | 0 | |
MAIN_CPSW2_0 | CPTS_RFT_CLK | MAIN_SYSCLK0 | 1 | CPSW2_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_CPSW2_0 | GMII_RFT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 2 | ||||
MAIN_CPSW2_0 | GMII1_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW2_0 | GMII1_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW2_0 | RGMII_MHZ_250_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 1 | ||||
MAIN_CPSW2_0 | RGMII_MHZ_5_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 50 | ||||
MAIN_CPSW2_0 | RGMII_MHZ_50_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 5 | ||||
MAIN_CPSW9_0 | CPPI_ICLK | MAIN_PLL_1.HSDIVOUT1_CLK | 1 | ||||
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | CPSW_CLKSEL[3:0] | 0 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | CPSW_CLKSEL[3:0] | 1 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MCU_CPTS0_RFT_CLK | 1 | CPSW_CLKSEL[3:0] | 2 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | CPTS0_RFT_CLK | 1 | CPSW_CLKSEL[3:0] | 3 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MCU_EXT_REFCLK0 | 1 | CPSW_CLKSEL[3:0] | 4 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | EXT_REFCLK1 | 1 | CPSW_CLKSEL[3:0] | 5 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 6 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 7 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 8 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 9 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 10 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 11 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 12 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | CPSW_CLKSEL[3:0] | 13 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | CPSW_CLKSEL[3:0] | 14 | 0 | |
MAIN_CPSW9_0 | CPTS_RFT_CLK | MAIN_SYSCLK0 | 1 | CPSW_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_CPSW9_0 | GMII_RFT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 2 | ||||
MAIN_CPSW9_0 | GMII1_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII1_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII2_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII2_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII3_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII3_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII4_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII4_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII5_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII5_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII6_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII6_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII7_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII7_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII8_MR_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | GMII8_MT_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 10 | ||||
MAIN_CPSW9_0 | RGMII_MHZ_250_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 1 | ||||
MAIN_CPSW9_0 | RGMII_MHZ_5_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 50 | ||||
MAIN_CPSW9_0 | RGMII_MHZ_50_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 5 | ||||
MAIN_CSI_RX_0 | MAIN_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CSI_RX_0 | PPI_D_RX_ULPS_ESC | MAIN_DPHY_RX_0.PPI_D_RX_ULPS_ESC | 1 | ||||
MAIN_CSI_RX_0 | PPI_RX_BYTE_CLK | MAIN_DPHY_RX_0.PPI_RX_BYTE_CLK | 1 | ||||
MAIN_CSI_RX_0 | VBUS_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_RX_0 | VP_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | ||||
MAIN_CSI_RX_1 | MAIN_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CSI_RX_1 | PPI_D_RX_ULPS_ESC | MAIN_DPHY_RX_1.PPI_D_RX_ULPS_ESC | 1 | ||||
MAIN_CSI_RX_1 | PPI_RX_BYTE_CLK | MAIN_DPHY_RX_1.PPI_RX_BYTE_CLK | 1 | ||||
MAIN_CSI_RX_1 | VBUS_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_RX_1 | VP_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | ||||
MAIN_CSI_RX_2 | MAIN_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CSI_RX_2 | PPI_D_RX_ULPS_ESC | MAIN_DPHY_RX_2.PPI_D_RX_ULPS_ESC | 1 | ||||
MAIN_CSI_RX_2 | PPI_RX_BYTE_CLK | MAIN_DPHY_RX_2.PPI_RX_BYTE_CLK | 1 | ||||
MAIN_CSI_RX_2 | VBUS_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_RX_2 | VP_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | ||||
MAIN_CSI_TX_0 | DPHY_TXBYTECLKHS | MAIN_DPHY_TX_0.IP2_PPI_TXBYTECLKHS_CL_CLK | 1 | ||||
MAIN_CSI_TX_0 | ESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_CSI_TX_0 | MAIN_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CSI_TX_0 | VBUS_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_TX_1 | DPHY_TXBYTECLKHS | MAIN_DPHY_TX_1.IP2_PPI_TXBYTECLKHS_CL_CLK | 1 | ||||
MAIN_CSI_TX_1 | ESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_CSI_TX_1 | MAIN_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CSI_TX_1 | VBUS_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_DCC_0 | INPUT1_CLK | MAIN_SYSCLK0 | 2 | DCC_CLKSRC1 | 0 | 0 | 250 MHz |
MAIN_DCC_0 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_0 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_0 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT3_CLK | 1 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_0 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_0 | INPUT1_CLK | HFOSC_0 | 1 | DCC_CLKSRC1 | 5 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_0 | INPUT1_CLK | HFOSC_1 | 1 | DCC_CLKSRC1 | 6 | 0 | [19.2, - 27] MHz |
MAIN_DCC_0 | INPUT1_CLK | MAIN_SYSCLK0 | 1 | DCC_CLKSRC1 | 7 | 0 | 500 MHz |
MAIN_DCC_0 | INPUT1_CLK | MAIN_DSS_EDP_0.PHY_LN0_TXCLK | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_0 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_0 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_0 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_1 | INPUT1_CLK | MAIN_SYSCLK0 | 4 | DCC_CLKSRC1 | 0 | 0 | 125 MHz |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT7_CLK | 1 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_1 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT6_CLK | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_1 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_1 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_1 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_1 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_2 | INPUT1_CLK | MAIN_SYSCLK0 | 4 | DCC_CLKSRC1 | 0 | 0 | 125 MHz |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT7_CLK | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 2 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_2 | INPUT1_CLK | MAIN_PLL_3.HSDIVOUT0_CLK | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_2 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_2 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_2 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_2 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_3 | INPUT1_CLK | MAIN_SYSCLK0 | 4 | DCC_CLKSRC1 | 0 | 0 | 125 MHz |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_4.HSDIVOUT0_CLK | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_5.HSDIVOUT0_CLK | 2 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_5.HSDIVOUT1_CLK | 2 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_9.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_6.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_3 | INPUT1_CLK | MAIN_PLL_8.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_3 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_3 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_3 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_3 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_4 | INPUT1_CLK | MAIN_SYSCLK0 | 2 | DCC_CLKSRC1 | 0 | 0 | 250 MHz |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_0.HSDIVOUT1_CLK | 2 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_28.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_12.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_26.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_14.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_14.HSDIVOUT1_CLK | 4 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_27.HSDIVOUT0_CLK | 4 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_4 | INPUT1_CLK | MAIN_PLL_16.HSDIVOUT0_CLK | 2 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_4 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_4 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_4 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_4 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_5 | INPUT1_CLK | MAIN_SYSCLK0 | 1 | DCC_CLKSRC1 | 0 | 0 | 500 MHz |
MAIN_DCC_5 | INPUT1_CLK | MAIN_PLL_19.HSDIVOUT0_CLK | 2 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_5 | INPUT1_CLK | MAIN_PLL_17.HSDIVOUT0_CLK | 2 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_5 | INPUT1_CLK | MAIN_PLL_25.HSDIVOUT0_CLK | 2 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_5 | INPUT1_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 2 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_5 | INPUT1_CLK | GPMC0_CLK | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_5 | INPUT1_CLK | MAIN_MCASP_4.MCASP_AHCLKX_POUT | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_5 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_5 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_5 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_5 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_6 | INPUT1_CLK | MAIN_SYSCLK0 | 4 | DCC_CLKSRC1 | 0 | 0 | 125 MHz |
MAIN_DCC_6 | INPUT1_CLK | MCASP0_ACLKX | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP0_ACLKR | 1 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP1_ACLKX | 1 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP1_ACLKR | 1 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP2_ACLKX | 1 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP2_ACLKR | 1 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP3_ACLKX | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_6 | INPUT1_CLK | MCASP3_ACLKR | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_6 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_6 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_6 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_6 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_7 | INPUT1_CLK | MAIN_SYSCLK0 | 2 | DCC_CLKSRC1 | 0 | 0 | 250 MHz |
MAIN_DCC_7 | INPUT1_CLK | AUDIO_EXT_REFCLK0 | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_7 | INPUT1_CLK | AUDIO_EXT_REFCLK1 | 1 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_7 | INPUT1_CLK | MAIN_PLL_14.HSDIVOUT2_CLK | 4 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_7 | INPUT1_CLK | VOUT0_EXTPCLKIN | 1 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_7 | INPUT1_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_7 | INPUT1_CLK | CPTS0_RFT_CLK | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_7 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_7 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_7 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_7 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_8 | INPUT1_CLK | MAIN_SYSCLK0 | 2 | DCC_CLKSRC1 | 0 | 0 | 250 MHz |
MAIN_DCC_8 | INPUT1_CLK | CLK_32K | 1 | DCC_CLKSRC1 | 1 | 0 | 32 KHz |
MAIN_DCC_8 | INPUT1_CLK | LFOSC | 1 | DCC_CLKSRC1 | 2 | 0 | 32 KHz |
MAIN_DCC_8 | INPUT1_CLK | MCU_EXT_REFCLK0 | 1 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_8 | INPUT1_CLK | MAIN_DPHY_RX_0.PPI_RX_BYTE_CLK | 1 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_8 | INPUT1_CLK | MAIN_DPHY_RX_1.PPI_RX_BYTE_CLK | 1 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_8 | INPUT1_CLK | MAIN_DPHY_RX_2.PPI_RX_BYTE_CLK | 1 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_8 | INPUT1_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_8 | INPUT1_CLK | MAIN_PLL_3.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 8 | 0 | |
MAIN_DCC_8 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_8 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_8 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_8 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DCC_9 | INPUT1_CLK | MAIN_SYSCLK0 | 2 | DCC_CLKSRC1 | 0 | 0 | 250 MHz |
MAIN_DCC_9 | INPUT1_CLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | DCC_CLKSRC1 | 1 | 0 | |
MAIN_DCC_9 | INPUT1_CLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | DCC_CLKSRC1 | 2 | 0 | |
MAIN_DCC_9 | INPUT1_CLK | RGMII1_RXC | 1 | DCC_CLKSRC1 | 3 | 0 | |
MAIN_DCC_9 | INPUT1_CLK | MAIN_MCASP_4.MCASP_AHCLKR_POUT | 1 | DCC_CLKSRC1 | 4 | 0 | |
MAIN_DCC_9 | INPUT1_CLK | RMII_REF_CLK | 1 | DCC_CLKSRC1 | 5 | 0 | |
MAIN_DCC_9 | INPUT1_CLK | MAIN_PLL_4.HSDIVOUT1_CLK | 1 | DCC_CLKSRC1 | 6 | 0 | |
MAIN_DCC_9 | INPUT1_CLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | DCC_CLKSRC1 | 7 | 0 | |
MAIN_DCC_9 | INPUT0_CLK | HFOSC_0 | 1 | DCC_CLKSRC0 | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DCC_9 | INPUT0_CLK | HFOSC_1 | 1 | DCC_CLKSRC0 | 1 | 0 | [19.2, - 27] MHz |
MAIN_DCC_9 | INPUT0_CLK | CLK_12M_RC | 1 | DCC_CLKSRC0 | 2 | 0 | 12 MHz |
MAIN_DCC_9 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_0 | DDRSS_FCLK | MAIN_PLL_12.HSDIVOUT0_CLK | 1 | ||||
MAIN_DDR_0 | DDRSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_0 | DDRSS_VBUS_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 4 | ||||
MAIN_DDR_0 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_DDR_1 | DDRSS_FCLK | MAIN_PLL_26.HSDIVOUT0_CLK | 1 | ||||
MAIN_DDR_1 | DDRSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_1 | DDRSS_VBUS_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 4 | ||||
MAIN_DDR_1 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_DDR_2 | DDRSS_FCLK | MAIN_PLL_27.HSDIVOUT0_CLK | 1 | ||||
MAIN_DDR_2 | DDRSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_2 | DDRSS_VBUS_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 4 | ||||
MAIN_DDR_2 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_DDR_3 | DDRSS_FCLK | MAIN_PLL_28.HSDIVOUT0_CLK | 1 | ||||
MAIN_DDR_3 | DDRSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_3 | DDRSS_VBUS_CLK | MAIN_PLL_7.HSDIVOUT0_CLK | 4 | ||||
MAIN_DDR_3 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_DMPAC_0 | MAIN_CLK | MAIN_PLL_25.HSDIVOUT0_CLK | 1 | ||||
MAIN_DPHY_RX_0 | MAIN_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DPHY_RX_1 | MAIN_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DPHY_RX_2 | MAIN_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DPHY_TX_0 | CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DPHY_TX_0 | DPHY_REF_CLK | HFOSC_0 | 1 | DPHY0_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DPHY_TX_0 | DPHY_REF_CLK | HFOSC_1 | 1 | DPHY0_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_DPHY_TX_0 | DPHY_REF_CLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | DPHY0_CLKSEL[1:0] | 2 | 0 | |
MAIN_DPHY_TX_0 | DPHY_REF_CLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | DPHY0_CLKSEL[1:0] | 3 | 0 | |
MAIN_DPHY_TX_0 | IP1_PPI_M_TXCLKESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DPHY_TX_0 | IP2_PPI_M_TXCLKESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DPHY_TX_0 | PSM_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DPHY_TX_1 | CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DPHY_TX_1 | DPHY_REF_CLK | HFOSC_0 | 1 | DPHY1_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_DPHY_TX_1 | DPHY_REF_CLK | HFOSC_1 | 1 | DPHY1_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_DPHY_TX_1 | DPHY_REF_CLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | DPHY1_CLKSEL[1:0] | 2 | 0 | |
MAIN_DPHY_TX_1 | DPHY_REF_CLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | DPHY1_CLKSEL[1:0] | 3 | 0 | |
MAIN_DPHY_TX_1 | IP1_PPI_M_TXCLKESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DPHY_TX_1 | PSM_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DSS_0 | DSS_FUNC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | ||||
MAIN_DSS_0 | DSS_INST0_DPI_0_DIV2_PCLK | MAIN_PLL_16.HSDIVOUT0_CLK | 2 | [] | 0 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_0_DIV2_PCLK | DPI_1_PCLK_SEL.OUT0 | 2 | [] | 1 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_0_PCLK | MAIN_PLL_16.HSDIVOUT0_CLK | 1 | [] | 0 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_0_PCLK | DPI_1_PCLK_SEL.OUT0 | 1 | [] | 1 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_1_PCLK | MAIN_PLL_17.HSDIVOUT0_CLK | 1 | DSS_DISPC0_CLKSEL1[1:0] | 0 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_1_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL1[1:0] | 1 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_1_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL1[1:0] | 2 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_1_PCLK | MAIN_PLL_16.HSDIVOUT0_CLK | 1 | DSS_DISPC0_CLKSEL1[1:0] | 3 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_2_DIV2_PCLK | DPI_2_PCLK_SEL.OUT0 | 2 | [] | 0 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_2_DIV2_PCLK | DPI0_EXT_CLKSEL.OUT0 | 2 | [] | 1 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_2_PCLK | DPI_2_PCLK_SEL.OUT0 | 1 | [] | 0 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_2_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | [] | 1 | -1 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | MAIN_PLL_16.HSDIVOUT1_CLK | 1 | DSS_DISPC0_CLKSEL3[2:0] | 0 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | MAIN_PLL_17.HSDIVOUT1_CLK | 1 | DSS_DISPC0_CLKSEL3[2:0] | 1 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | MAIN_PLL_17.HSDIVOUT1_CLK | 1 | DSS_DISPC0_CLKSEL3[2:0] | 2 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL3[2:0] | 3 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL3[2:0] | 4 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL3[2:0] | 5 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL3[2:0] | 6 | 0 | |
MAIN_DSS_0 | DSS_INST0_DPI_3_PCLK | DPI0_EXT_CLKSEL.OUT0 | 1 | DSS_DISPC0_CLKSEL3[2:0] | 7 | 0 | |
MAIN_DSS_DSI_0 | DSI_DPHY_0_RX_ESC_CLK | MAIN_DPHY_TX_0.IP1_PPI_M_RXCLKESC_CLK | 1 | ||||
MAIN_DSS_DSI_0 | DSI_DPHY_0_TX_ESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DSS_DSI_0 | DSI_DPI_0_CLK | MAIN_DSS_0.DSS_INST0_DPI_2_OUT_CLK | 1 | ||||
MAIN_DSS_DSI_0 | DSI_PPI_0_TXBYTECLKHS_CL_CLK | MAIN_DPHY_TX_0.IP1_PPI_TXBYTECLKHS_CL_CLK | 1 | ||||
MAIN_DSS_DSI_0 | DSI_SYS_CLK | MAIN_SYSCLK0 | 1 | 0 | 500 MHz | ||
MAIN_DSS_DSI_0 | DSI_SYS_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | 1 | |||
MAIN_DSS_DSI_0 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_DSS_DSI_1 | DSI_DPHY_0_RX_ESC_CLK | MAIN_DPHY_TX_1.IP1_PPI_M_RXCLKESC_CLK | 1 | ||||
MAIN_DSS_DSI_1 | DSI_DPHY_0_TX_ESC_CLK | MAIN_PLL_1.HSDIVOUT8_CLK | 1 | ||||
MAIN_DSS_DSI_1 | DSI_DPI_0_CLK | MAIN_DSS_0.DSS_INST0_PARA_1_OUT_CLK | 1 | 2 | |||
MAIN_DSS_DSI_1 | DSI_DPI_0_CLK | MAIN_DSS_0.DSS_INST0_PARA_3_OUT_CLK | 1 | 8 | |||
MAIN_DSS_DSI_1 | DSI_PPI_0_TXBYTECLKHS_CL_CLK | MAIN_DPHY_TX_1.IP1_PPI_TXBYTECLKHS_CL_CLK | 1 | ||||
MAIN_DSS_DSI_1 | DSI_SYS_CLK | MAIN_SYSCLK0 | 1 | 0 | 500 MHz | ||
MAIN_DSS_DSI_1 | DSI_SYS_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | 1 | |||
MAIN_DSS_DSI_1 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_DSS_EDP_0 | AIF_I2S_CLK | MAIN_MCASP_4.MCASP_ACLKX_POUT | 1 | ||||
MAIN_DSS_EDP_0 | DPI_2_2X_CLK | MAIN_DSS_0.DSS_INST0_DPI_0_OUT_2X_CLK | 1 | ||||
MAIN_DSS_EDP_0 | DPI_2_CLK | MAIN_DSS_0.DSS_INST0_DPI_0_OUT_CLK | 1 | ||||
MAIN_DSS_EDP_0 | DPI_3_CLK | MAIN_DSS_0.DSS_INST0_DPI_1_OUT_CLK | 1 | ||||
MAIN_DSS_EDP_0 | DPI_4_CLK | MAIN_DSS_0.DSS_INST0_DPI_2_OUT_CLK | 1 | ||||
MAIN_DSS_EDP_0 | DPI_5_CLK | MAIN_DSS_0.DSS_INST0_DPI_3_OUT_CLK | 1 | ||||
MAIN_DSS_EDP_0 | DPTX_CLK | MAIN_SYSCLK0 | 1 | [] | 0 | -1 | 500 MHz |
MAIN_DSS_EDP_0 | DPTX_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | [] | 1 | -1 | |
MAIN_DSS_EDP_0 | PHY_LN0_REFCLK | MAIN_SERDES_4.IP1_LN0_REFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN0_RXCLK | MAIN_SERDES_4.IP1_LN0_RXCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN0_RXFCLK | MAIN_SERDES_4.IP1_LN0_RXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN0_TXFCLK | MAIN_SERDES_4.IP1_LN0_TXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN0_TXMCLK | MAIN_SERDES_4.IP1_LN0_TXMCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN1_REFCLK | MAIN_SERDES_4.IP1_LN1_REFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN1_RXCLK | MAIN_SERDES_4.IP1_LN1_RXCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN1_RXFCLK | MAIN_SERDES_4.IP1_LN1_RXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN1_TXFCLK | MAIN_SERDES_4.IP1_LN1_TXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN1_TXMCLK | MAIN_SERDES_4.IP1_LN1_TXMCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN2_REFCLK | MAIN_SERDES_4.IP1_LN2_REFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN2_RXCLK | MAIN_SERDES_4.IP1_LN2_RXCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN2_RXFCLK | MAIN_SERDES_4.IP1_LN2_RXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN2_TXFCLK | MAIN_SERDES_4.IP1_LN2_TXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN2_TXMCLK | MAIN_SERDES_4.IP1_LN2_TXMCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN3_REFCLK | MAIN_SERDES_4.IP1_LN3_REFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN3_RXCLK | MAIN_SERDES_4.IP1_LN3_RXCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN3_RXFCLK | MAIN_SERDES_4.IP1_LN3_RXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN3_TXFCLK | MAIN_SERDES_4.IP1_LN3_TXFCLK | 1 | ||||
MAIN_DSS_EDP_0 | PHY_LN3_TXMCLK | MAIN_SERDES_4.IP1_LN3_TXMCLK | 1 | ||||
MAIN_DSS_EDP_0 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_ECAP_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_ECAP_1 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_ECAP_2 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EMMC4_0 | EMMCSDSS_FCLK | MAIN_PLL_0.HSDIVOUT2_CLK | 1 | EMMC1_CLKSEL[1:0] | 0 | 1 | |
MAIN_EMMC4_0 | EMMCSDSS_FCLK | MAIN_PLL_1.HSDIVOUT2_CLK | 1 | EMMC1_CLKSEL[1:0] | 1 | 1 | |
MAIN_EMMC4_0 | EMMCSDSS_FCLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | EMMC1_CLKSEL[1:0] | 2 | 1 | |
MAIN_EMMC4_0 | EMMCSDSS_FCLK | MAIN_PLL_3.HSDIVOUT2_CLK | 1 | EMMC1_CLKSEL[1:0] | 3 | 1 | |
MAIN_EMMC4_0 | EMMCSDSS_ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_EMMC8_0 | EMMCSS_FCLK | MAIN_PLL_0.HSDIVOUT2_CLK | 1 | EMMC0_CLKSEL[1:0] | 0 | 0 | |
MAIN_EMMC8_0 | EMMCSS_FCLK | MAIN_PLL_1.HSDIVOUT2_CLK | 1 | EMMC0_CLKSEL[1:0] | 1 | 0 | |
MAIN_EMMC8_0 | EMMCSS_FCLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | EMMC0_CLKSEL[1:0] | 2 | 0 | |
MAIN_EMMC8_0 | EMMCSS_FCLK | MAIN_PLL_3.HSDIVOUT2_CLK | 1 | EMMC0_CLKSEL[1:0] | 3 | 0 | |
MAIN_EMMC8_0 | EMMCSS_ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_EPWM_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EPWM_1 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EPWM_2 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EPWM_3 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EPWM_4 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EPWM_5 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EQEP_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EQEP_1 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EQEP_2 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_ESM_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_GPIO_0 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_GPIO_2 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_GPIO_4 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_GPIO_6 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_GPMC_0 | FCLK | MAIN_PLL_0.HSDIVOUT3_CLK | 1 | GPMC_CLKSEL[1:0] | 0 | 0 | |
MAIN_GPMC_0 | FCLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | GPMC_CLKSEL[1:0] | 1 | 0 | |
MAIN_GPMC_0 | FCLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | GPMC_CLKSEL[1:0] | 2 | 0 | |
MAIN_GPMC_0 | FCLK | MAIN_SYSCLK0 | 1 | GPMC_CLKSEL[1:0] | 3 | 0 | 500 MHz |
MAIN_GPMC_0 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_GPMC_0 | PI_GPMC_RET_CLK | GPMC0_CLK | 1 | ||||
MAIN_GPU_0 | GPU0_CLK | MAIN_PLL_6.HSDIVOUT0_CLK | 1 | ||||
MAIN_GPU_0 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_GTC_0 | GTC_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | GTC_CLKSEL[3:0] | 0 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | GTC_CLKSEL[3:0] | 1 | 0 | |
MAIN_GTC_0 | GTC_CLK | MCU_CPTS0_RFT_CLK | 1 | GTC_CLKSEL[3:0] | 2 | 0 | |
MAIN_GTC_0 | GTC_CLK | CPTS0_RFT_CLK | 1 | GTC_CLKSEL[3:0] | 3 | 0 | |
MAIN_GTC_0 | GTC_CLK | MCU_EXT_REFCLK0 | 1 | GTC_CLKSEL[3:0] | 4 | 0 | |
MAIN_GTC_0 | GTC_CLK | EXT_REFCLK1 | 1 | GTC_CLKSEL[3:0] | 5 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | GTC_CLKSEL[3:0] | 6 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | GTC_CLKSEL[3:0] | 7 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | GTC_CLKSEL[3:0] | 8 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | GTC_CLKSEL[3:0] | 9 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | GTC_CLKSEL[3:0] | 10 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | GTC_CLKSEL[3:0] | 11 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | GTC_CLKSEL[3:0] | 12 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | GTC_CLKSEL[3:0] | 13 | 0 | |
MAIN_GTC_0 | GTC_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | GTC_CLKSEL[3:0] | 14 | 0 | |
MAIN_GTC_0 | GTC_CLK | MAIN_SYSCLK0 | 1 | GTC_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_GTC_0 | VBUSP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_HYPERLINK_0 | V0_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_HYPERLINK_0 | V0_RXPM_CLK | HYP0_RXPMCLK | 1 | ||||
MAIN_HYPERLINK_0 | V0_TXFL_CLK | HYP0_TXFLCLK | 1 | ||||
MAIN_HYPERLINK_0 | V1_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_I2C_0 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_0 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_I2C_1 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_1 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_I2C_2 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_2 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_I2C_3 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_3 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_I2C_4 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_4 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_I2C_5 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_5 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_I2C_6 | OCP_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_I2C_6 | SYS_CLK | MAIN_PLL_1.HSDIVOUT0_CLK | 2 | ||||
MAIN_MCANSS_0 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN0_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_0 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN0_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_0 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN0_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_0 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN0_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_0 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_1 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN1_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_1 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN1_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_1 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN1_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_1 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN1_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_1 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_2 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN2_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_2 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN2_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_2 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN2_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_2 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN2_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_2 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_3 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN3_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_3 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN3_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_3 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN3_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_3 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN3_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_3 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_4 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN4_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_4 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN4_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_4 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN4_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_4 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN4_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_4 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_5 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN5_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_5 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN5_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_5 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN5_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_5 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN5_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_5 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_6 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN6_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_6 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN6_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_6 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN6_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_6 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN6_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_6 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_7 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN7_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_7 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN7_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_7 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN7_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_7 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN7_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_7 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_8 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN8_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_8 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN8_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_8 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN8_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_8 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN8_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_8 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_9 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN9_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_9 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN9_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_9 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN9_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_9 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN9_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_9 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_10 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN10_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_10 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN10_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_10 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN10_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_10 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN10_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_10 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_11 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN11_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_11 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN11_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_11 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN11_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_11 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN11_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_11 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_12 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN12_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_12 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN12_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_12 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN12_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_12 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN12_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_12 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_13 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN13_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_13 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN13_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_13 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN13_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_13 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN13_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_13 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_14 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN14_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_14 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN14_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_14 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN14_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_14 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN14_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_14 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_15 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN15_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_15 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN15_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_15 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN15_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_15 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN15_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_15 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_16 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN16_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_16 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN16_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_16 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN16_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_16 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN16_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_16 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_17 | MCANSS_FCLK | MAIN_PLL_0.HSDIVOUT4_CLK | 1 | MCAN17_CLKSEL[1:0] | 0 | 0 | |
MAIN_MCANSS_17 | MCANSS_FCLK | MCU_EXT_REFCLK0 | 1 | MCAN17_CLKSEL[1:0] | 1 | 0 | |
MAIN_MCANSS_17 | MCANSS_FCLK | HFOSC_1 | 1 | MCAN17_CLKSEL[1:0] | 2 | 0 | [19.2, - 27] MHz |
MAIN_MCANSS_17 | MCANSS_FCLK | HFOSC_0 | 1 | MCAN17_CLKSEL[1:0] | 3 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_MCANSS_17 | MCANSS_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCASP_0 | AUX_CLK | MAIN_PLL_4.HSDIVOUT0_CLK | 1 | MCASP0_CLKSEL[2:0] | 0 | 0 | |
MAIN_MCASP_0 | AUX_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | MCASP0_CLKSEL[2:0] | 1 | 0 | |
MAIN_MCASP_0 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT | 1 | MCASP0_CLKSEL[2:0] | 4 | 0 | |
MAIN_MCASP_0 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_1 | 1 | MCASP0_CLKSEL[2:0] | 5 | 0 | |
MAIN_MCASP_0 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_2 | 1 | MCASP0_CLKSEL[2:0] | 6 | 0 | |
MAIN_MCASP_0 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_3 | 1 | MCASP0_CLKSEL[2:0] | 7 | 0 | |
MAIN_MCASP_0 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_MCASP_1 | AUX_CLK | MAIN_PLL_4.HSDIVOUT0_CLK | 1 | MCASP1_CLKSEL[2:0] | 0 | 0 | |
MAIN_MCASP_1 | AUX_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | MCASP1_CLKSEL[2:0] | 1 | 0 | |
MAIN_MCASP_1 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT | 1 | MCASP1_CLKSEL[2:0] | 4 | 0 | |
MAIN_MCASP_1 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_1 | 1 | MCASP1_CLKSEL[2:0] | 5 | 0 | |
MAIN_MCASP_1 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_2 | 1 | MCASP1_CLKSEL[2:0] | 6 | 0 | |
MAIN_MCASP_1 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_3 | 1 | MCASP1_CLKSEL[2:0] | 7 | 0 | |
MAIN_MCASP_1 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_MCASP_2 | AUX_CLK | MAIN_PLL_4.HSDIVOUT0_CLK | 1 | MCASP2_CLKSEL[2:0] | 0 | 0 | |
MAIN_MCASP_2 | AUX_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | MCASP2_CLKSEL[2:0] | 1 | 0 | |
MAIN_MCASP_2 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT | 1 | MCASP2_CLKSEL[2:0] | 4 | 0 | |
MAIN_MCASP_2 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_1 | 1 | MCASP2_CLKSEL[2:0] | 5 | 0 | |
MAIN_MCASP_2 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_2 | 1 | MCASP2_CLKSEL[2:0] | 6 | 0 | |
MAIN_MCASP_2 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_3 | 1 | MCASP2_CLKSEL[2:0] | 7 | 0 | |
MAIN_MCASP_2 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_MCASP_3 | AUX_CLK | MAIN_PLL_4.HSDIVOUT0_CLK | 1 | MCASP3_CLKSEL[2:0] | 0 | 0 | |
MAIN_MCASP_3 | AUX_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | MCASP3_CLKSEL[2:0] | 1 | 0 | |
MAIN_MCASP_3 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT | 1 | MCASP3_CLKSEL[2:0] | 4 | 0 | |
MAIN_MCASP_3 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_1 | 1 | MCASP3_CLKSEL[2:0] | 5 | 0 | |
MAIN_MCASP_3 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_2 | 1 | MCASP3_CLKSEL[2:0] | 6 | 0 | |
MAIN_MCASP_3 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_3 | 1 | MCASP3_CLKSEL[2:0] | 7 | 0 | |
MAIN_MCASP_3 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_MCASP_4 | AUX_CLK | MAIN_PLL_4.HSDIVOUT0_CLK | 1 | MCASP4_CLKSEL[2:0] | 0 | 0 | |
MAIN_MCASP_4 | AUX_CLK | MAIN_PLL_2.HSDIVOUT2_CLK | 1 | MCASP4_CLKSEL[2:0] | 1 | 0 | |
MAIN_MCASP_4 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT | 1 | MCASP4_CLKSEL[2:0] | 4 | 0 | |
MAIN_MCASP_4 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_1 | 1 | MCASP4_CLKSEL[2:0] | 5 | 0 | |
MAIN_MCASP_4 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_2 | 1 | MCASP4_CLKSEL[2:0] | 6 | 0 | |
MAIN_MCASP_4 | AUX_CLK | MAIN_ATL_0.ATL_IO_PORT_ATCLK_OUT_3 | 1 | MCASP4_CLKSEL[2:0] | 7 | 0 | |
MAIN_MCASP_4 | ICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_PCIE_0 | FICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | PCIE0_CLKSEL[3:0] | 0 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | PCIE0_CLKSEL[3:0] | 1 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MCU_CPTS0_RFT_CLK | 1 | PCIE0_CLKSEL[3:0] | 2 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | CPTS0_RFT_CLK | 1 | PCIE0_CLKSEL[3:0] | 3 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MCU_EXT_REFCLK0 | 1 | PCIE0_CLKSEL[3:0] | 4 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | EXT_REFCLK1 | 1 | PCIE0_CLKSEL[3:0] | 5 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 6 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 7 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 8 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 9 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 10 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 11 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 12 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | PCIE0_CLKSEL[3:0] | 13 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | PCIE0_CLKSEL[3:0] | 14 | 0 | |
MAIN_PCIE_0 | PCIE_CPTS_RCLK_CLK | MAIN_SYSCLK0 | 1 | PCIE0_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_PCIE_0 | PCIE_PM_CLK | CLK_12M_RC | 1 | 12 MHz | |||
MAIN_PCIE_1 | FICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | PCIE1_CLKSEL[3:0] | 0 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | PCIE1_CLKSEL[3:0] | 1 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MCU_CPTS0_RFT_CLK | 1 | PCIE1_CLKSEL[3:0] | 2 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | CPTS0_RFT_CLK | 1 | PCIE1_CLKSEL[3:0] | 3 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MCU_EXT_REFCLK0 | 1 | PCIE1_CLKSEL[3:0] | 4 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | EXT_REFCLK1 | 1 | PCIE1_CLKSEL[3:0] | 5 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 6 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 7 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 8 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 9 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 10 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 11 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 12 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | PCIE1_CLKSEL[3:0] | 13 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | PCIE1_CLKSEL[3:0] | 14 | 0 | |
MAIN_PCIE_1 | PCIE_CPTS_RCLK_CLK | MAIN_SYSCLK0 | 1 | PCIE1_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_PCIE_1 | PCIE_PM_CLK | CLK_12M_RC | 1 | 12 MHz | |||
MAIN_PCIE_2 | FICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | PCIE2_CLKSEL[3:0] | 0 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | PCIE2_CLKSEL[3:0] | 1 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MCU_CPTS0_RFT_CLK | 1 | PCIE2_CLKSEL[3:0] | 2 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | CPTS0_RFT_CLK | 1 | PCIE2_CLKSEL[3:0] | 3 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MCU_EXT_REFCLK0 | 1 | PCIE2_CLKSEL[3:0] | 4 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | EXT_REFCLK1 | 1 | PCIE2_CLKSEL[3:0] | 5 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 6 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 7 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 8 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 9 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 10 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 11 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 12 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | PCIE2_CLKSEL[3:0] | 13 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | PCIE2_CLKSEL[3:0] | 14 | 0 | |
MAIN_PCIE_2 | PCIE_CPTS_RCLK_CLK | MAIN_SYSCLK0 | 1 | PCIE2_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_PCIE_2 | PCIE_PM_CLK | CLK_12M_RC | 1 | 12 MHz | |||
MAIN_PCIE_3 | FICLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_3.HSDIVOUT1_CLK | 1 | PCIE3_CLKSEL[3:0] | 0 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_PLL_0.HSDIVOUT6_CLK | 1 | PCIE3_CLKSEL[3:0] | 1 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MCU_CPTS0_RFT_CLK | 1 | PCIE3_CLKSEL[3:0] | 2 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | CPTS0_RFT_CLK | 1 | PCIE3_CLKSEL[3:0] | 3 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MCU_EXT_REFCLK0 | 1 | PCIE3_CLKSEL[3:0] | 4 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | EXT_REFCLK1 | 1 | PCIE3_CLKSEL[3:0] | 5 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN0_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 6 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN1_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 7 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN2_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 8 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP2_LN3_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 9 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN0_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 10 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP2_LN1_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 11 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_0.IP1_LN2_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 12 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SERDES_1.IP3_LN2_TXMCLK | 1 | PCIE3_CLKSEL[3:0] | 13 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MCU_PLL_2.HSDIVOUT1_CLK | 1 | PCIE3_CLKSEL[3:0] | 14 | 0 | |
MAIN_PCIE_3 | PCIE_CPTS_RCLK_CLK | MAIN_SYSCLK0 | 1 | PCIE3_CLKSEL[3:0] | 15 | 0 | 500 MHz |
MAIN_PCIE_3 | PCIE_PM_CLK | CLK_12M_RC | 1 | 12 MHz | |||
MAIN_R5FSS_0_CORE_0 | FCLK | MAIN_PLL_14.HSDIVOUT0_CLK | 1 | ||||
MAIN_R5FSS_0_CORE_1 | FCLK | MAIN_PLL_14.HSDIVOUT0_CLK | 1 | ||||
MAIN_R5FSS_1_CORE_0 | FCLK | MAIN_PLL_14.HSDIVOUT1_CLK | 1 | ||||
MAIN_R5FSS_1_CORE_1 | FCLK | MAIN_PLL_14.HSDIVOUT1_CLK | 1 | ||||
MAIN_R5FSS_2_CORE_0 | FCLK | MAIN_PLL_14.HSDIVOUT2_CLK | 1 | ||||
MAIN_R5FSS_2_CORE_1 | FCLK | MAIN_PLL_14.HSDIVOUT2_CLK | 1 | ||||
MAIN_RTI_A72SS_0_CORE_0 | FCLK | HFOSC_0 | 1 | WWD0_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | LFOSC | 1 | WWD0_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | CLK_12M_RC | 1 | WWD0_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | CLK_32K | 1 | WWD0_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD0_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD0_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD0_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD0_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_0_CORE_1 | FCLK | HFOSC_0 | 1 | WWD1_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | LFOSC | 1 | WWD1_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | CLK_12M_RC | 1 | WWD1_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | CLK_32K | 1 | WWD1_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD1_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD1_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD1_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD1_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_0_CORE_2 | FCLK | HFOSC_0 | 1 | WWD2_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | LFOSC | 1 | WWD2_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | CLK_12M_RC | 1 | WWD2_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | CLK_32K | 1 | WWD2_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | HFOSC_1 | 1 | WWD2_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | HFOSC_1 | 1 | WWD2_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | HFOSC_1 | 1 | WWD2_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_2 | FCLK | HFOSC_1 | 1 | WWD2_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_2 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_0_CORE_3 | FCLK | HFOSC_0 | 1 | WWD3_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | LFOSC | 1 | WWD3_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | CLK_12M_RC | 1 | WWD3_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | CLK_32K | 1 | WWD3_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | HFOSC_1 | 1 | WWD3_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | HFOSC_1 | 1 | WWD3_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | HFOSC_1 | 1 | WWD3_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_3 | FCLK | HFOSC_1 | 1 | WWD3_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_0_CORE_3 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_1_CORE_0 | FCLK | HFOSC_0 | 1 | WWD4_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | LFOSC | 1 | WWD4_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | CLK_12M_RC | 1 | WWD4_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | CLK_32K | 1 | WWD4_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD4_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD4_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD4_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD4_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_1_CORE_1 | FCLK | HFOSC_0 | 1 | WWD5_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | LFOSC | 1 | WWD5_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | CLK_12M_RC | 1 | WWD5_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | CLK_32K | 1 | WWD5_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD5_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD5_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD5_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD5_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_1_CORE_2 | FCLK | HFOSC_0 | 1 | WWD6_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | LFOSC | 1 | WWD6_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | CLK_12M_RC | 1 | WWD6_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | CLK_32K | 1 | WWD6_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | HFOSC_1 | 1 | WWD6_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | HFOSC_1 | 1 | WWD6_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | HFOSC_1 | 1 | WWD6_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_2 | FCLK | HFOSC_1 | 1 | WWD6_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_2 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_A72SS_1_CORE_3 | FCLK | HFOSC_0 | 1 | WWD7_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | LFOSC | 1 | WWD7_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | CLK_12M_RC | 1 | WWD7_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | CLK_32K | 1 | WWD7_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | HFOSC_1 | 1 | WWD7_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | HFOSC_1 | 1 | WWD7_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | HFOSC_1 | 1 | WWD7_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_3 | FCLK | HFOSC_1 | 1 | WWD7_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_A72SS_1_CORE_3 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_C71SS_0 | FCLK | HFOSC_0 | 1 | WWD16_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_C71SS_0 | FCLK | LFOSC | 1 | WWD16_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_C71SS_0 | FCLK | CLK_12M_RC | 1 | WWD16_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_C71SS_0 | FCLK | CLK_32K | 1 | WWD16_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_C71SS_0 | FCLK | HFOSC_1 | 1 | WWD16_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_0 | FCLK | HFOSC_1 | 1 | WWD16_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_0 | FCLK | HFOSC_1 | 1 | WWD16_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_0 | FCLK | HFOSC_1 | 1 | WWD16_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_C71SS_1 | FCLK | HFOSC_0 | 1 | WWD17_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_C71SS_1 | FCLK | LFOSC | 1 | WWD17_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_C71SS_1 | FCLK | CLK_12M_RC | 1 | WWD17_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_C71SS_1 | FCLK | CLK_32K | 1 | WWD17_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_C71SS_1 | FCLK | HFOSC_1 | 1 | WWD17_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_1 | FCLK | HFOSC_1 | 1 | WWD17_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_1 | FCLK | HFOSC_1 | 1 | WWD17_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_1 | FCLK | HFOSC_1 | 1 | WWD17_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_C71SS_2 | FCLK | HFOSC_0 | 1 | WWD18_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_C71SS_2 | FCLK | LFOSC | 1 | WWD18_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_C71SS_2 | FCLK | CLK_12M_RC | 1 | WWD18_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_C71SS_2 | FCLK | CLK_32K | 1 | WWD18_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_C71SS_2 | FCLK | HFOSC_1 | 1 | WWD18_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_2 | FCLK | HFOSC_1 | 1 | WWD18_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_2 | FCLK | HFOSC_1 | 1 | WWD18_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_2 | FCLK | HFOSC_1 | 1 | WWD18_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_2 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_C71SS_3 | FCLK | HFOSC_0 | 1 | WWD19_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_C71SS_3 | FCLK | LFOSC | 1 | WWD19_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_C71SS_3 | FCLK | CLK_12M_RC | 1 | WWD19_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_C71SS_3 | FCLK | CLK_32K | 1 | WWD19_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_C71SS_3 | FCLK | HFOSC_1 | 1 | WWD19_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_3 | FCLK | HFOSC_1 | 1 | WWD19_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_3 | FCLK | HFOSC_1 | 1 | WWD19_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_3 | FCLK | HFOSC_1 | 1 | WWD19_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_C71SS_3 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | HFOSC_0 | 1 | WWD28_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | LFOSC | 1 | WWD28_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | CLK_12M_RC | 1 | WWD28_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | CLK_32K | 1 | WWD28_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD28_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD28_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD28_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_0 | FCLK | HFOSC_1 | 1 | WWD28_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | HFOSC_0 | 1 | WWD29_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | LFOSC | 1 | WWD29_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | CLK_12M_RC | 1 | WWD29_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | CLK_32K | 1 | WWD29_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD29_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD29_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD29_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_1 | FCLK | HFOSC_1 | 1 | WWD29_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_0_CORE_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | HFOSC_0 | 1 | WWD30_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | LFOSC | 1 | WWD30_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | CLK_12M_RC | 1 | WWD30_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | CLK_32K | 1 | WWD30_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD30_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD30_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD30_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_0 | FCLK | HFOSC_1 | 1 | WWD30_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | HFOSC_0 | 1 | WWD31_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | LFOSC | 1 | WWD31_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | CLK_12M_RC | 1 | WWD31_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | CLK_32K | 1 | WWD31_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD31_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD31_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD31_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_1 | FCLK | HFOSC_1 | 1 | WWD31_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_1_CORE_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | HFOSC_0 | 1 | WWD32_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | LFOSC | 1 | WWD32_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | CLK_12M_RC | 1 | WWD32_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | CLK_32K | 1 | WWD32_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | HFOSC_1 | 1 | WWD32_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | HFOSC_1 | 1 | WWD32_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | HFOSC_1 | 1 | WWD32_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_0 | FCLK | HFOSC_1 | 1 | WWD32_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | HFOSC_0 | 1 | WWD33_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | LFOSC | 1 | WWD33_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | CLK_12M_RC | 1 | WWD33_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | CLK_32K | 1 | WWD33_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | HFOSC_1 | 1 | WWD33_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | HFOSC_1 | 1 | WWD33_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | HFOSC_1 | 1 | WWD33_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_1 | FCLK | HFOSC_1 | 1 | WWD33_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_R5FSS_2_CORE_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SA2_UL_0 | PKA_IN_CLK | MAIN_PLL_0.HSDIVOUT1_CLK | 1 | ||||
MAIN_SA2_UL_0 | X1_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SA2_UL_0 | X2_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_SERDES_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SERDES_0 | REFCLK | HFOSC_0 | 1 | SERDES0_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_SERDES_0 | REFCLK | HFOSC_1 | 1 | SERDES0_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_SERDES_0 | REFCLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | SERDES0_CLKSEL[1:0] | 2 | 0 | |
MAIN_SERDES_0 | REFCLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | SERDES0_CLKSEL[1:0] | 3 | 0 | |
MAIN_SERDES_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SERDES_1 | REFCLK | HFOSC_0 | 1 | SERDES1_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_SERDES_1 | REFCLK | HFOSC_1 | 1 | SERDES1_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_SERDES_1 | REFCLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | SERDES1_CLKSEL[1:0] | 2 | 0 | |
MAIN_SERDES_1 | REFCLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | SERDES1_CLKSEL[1:0] | 3 | 0 | |
MAIN_SERDES_2 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SERDES_2 | REFCLK | HFOSC_0 | 1 | SERDES2_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_SERDES_2 | REFCLK | HFOSC_1 | 1 | SERDES2_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_SERDES_2 | REFCLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | SERDES2_CLKSEL[1:0] | 2 | 0 | |
MAIN_SERDES_2 | REFCLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | SERDES2_CLKSEL[1:0] | 3 | 0 | |
MAIN_SERDES_4 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SERDES_4 | REFCLK | HFOSC_0 | 1 | SERDES4_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_SERDES_4 | REFCLK | HFOSC_1 | 1 | SERDES4_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_SERDES_4 | REFCLK | MAIN_PLL_3.HSDIVOUT4_CLK | 1 | SERDES4_CLKSEL[1:0] | 2 | 0 | |
MAIN_SERDES_4 | REFCLK | MAIN_PLL_2.HSDIVOUT4_CLK | 1 | SERDES4_CLKSEL[1:0] | 3 | 0 | |
MAIN_SPI_0 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_0 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_0 | IO_CLKSPII_CLK | SPI0_CLK | 1 | 0 | |||
MAIN_SPI_0 | IO_CLKSPII_CLK | MAIN_SPI_0.IO_CLKSPIO_CLK | 1 | 1 | |||
MAIN_SPI_1 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_1 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_1 | IO_CLKSPII_CLK | SPI1_CLK | 1 | 0 | |||
MAIN_SPI_1 | IO_CLKSPII_CLK | MAIN_SPI_1.IO_CLKSPIO_CLK | 1 | 1 | |||
MAIN_SPI_2 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_2 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_2 | IO_CLKSPII_CLK | SPI2_CLK | 1 | 0 | |||
MAIN_SPI_2 | IO_CLKSPII_CLK | MAIN_SPI_2.IO_CLKSPIO_CLK | 1 | 1 | |||
MAIN_SPI_3 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_3 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_3 | IO_CLKSPII_CLK | MAIN_SPI_3.IO_CLKSPIO_CLK | 1 | 0 | 0 | ||
MAIN_SPI_3 | IO_CLKSPII_CLK | SPI3_CLK_LPBK_MUX.OUT0 | 1 | 1 | 0 | ||
MAIN_SPI_4 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_4 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_4 | IO_CLKSPII_CLK | MAIN_SPI_4.IO_CLKSPIO_CLK | 1 | ||||
MAIN_SPI_5 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_5 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_5 | IO_CLKSPII_CLK | SPI5_CLK | 1 | 0 | |||
MAIN_SPI_5 | IO_CLKSPII_CLK | MAIN_SPI_5.IO_CLKSPIO_CLK | 1 | 1 | |||
MAIN_SPI_6 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_6 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_6 | IO_CLKSPII_CLK | SPI6_CLK | 1 | 0 | |||
MAIN_SPI_6 | IO_CLKSPII_CLK | MAIN_SPI_6.IO_CLKSPIO_CLK | 1 | 1 | |||
MAIN_SPI_7 | FCLK | MAIN_PLL_0.HSDIVOUT5_CLK | 1 | ||||
MAIN_SPI_7 | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SPI_7 | IO_CLKSPII_CLK | SPI7_CLK | 1 | 0 | |||
MAIN_SPI_7 | IO_CLKSPII_CLK | MAIN_SPI_7.IO_CLKSPIO_CLK | 1 | 1 | |||
MAIN_TIMER_0 | FCLK | HFOSC_0 | 1 | TIMER0_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_0 | FCLK | HFOSC_1 | 1 | TIMER0_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_0 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER0_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_0 | FCLK | CLK_12M_RC | 1 | TIMER0_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_0 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER0_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_0 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER0_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_0 | FCLK | EXT_REFCLK1 | 1 | TIMER0_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_0 | FCLK | LFOSC | 1 | TIMER0_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_0 | FCLK | CPTS0_RFT_CLK | 1 | TIMER0_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_0 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER0_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_0 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER0_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_0 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER0_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_0 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER0_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_0 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER0_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_0 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER0_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_0 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER0_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_0 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_1 | FCLK | MAIN_TIMER_CLKSEL.OUT1 | 1 | TIMER1_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_1 | FCLK | MAIN_TIMER_0.TIMER_PWM | 1 | TIMER1_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_1 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_2 | FCLK | HFOSC_0 | 1 | TIMER2_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_2 | FCLK | HFOSC_1 | 1 | TIMER2_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_2 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER2_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_2 | FCLK | CLK_12M_RC | 1 | TIMER2_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_2 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER2_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_2 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER2_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_2 | FCLK | EXT_REFCLK1 | 1 | TIMER2_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_2 | FCLK | LFOSC | 1 | TIMER2_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_2 | FCLK | CPTS0_RFT_CLK | 1 | TIMER2_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_2 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER2_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_2 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER2_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_2 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER2_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_2 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER2_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_2 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER2_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_2 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER2_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_2 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER2_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_2 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_3 | FCLK | MAIN_TIMER_CLKSEL.OUT3 | 1 | TIMER3_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_3 | FCLK | MAIN_TIMER_2.TIMER_PWM | 1 | TIMER3_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_3 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_4 | FCLK | HFOSC_0 | 1 | TIMER4_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_4 | FCLK | HFOSC_1 | 1 | TIMER4_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_4 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER4_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_4 | FCLK | CLK_12M_RC | 1 | TIMER4_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_4 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER4_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_4 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER4_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_4 | FCLK | EXT_REFCLK1 | 1 | TIMER4_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_4 | FCLK | LFOSC | 1 | TIMER4_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_4 | FCLK | CPTS0_RFT_CLK | 1 | TIMER4_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_4 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER4_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_4 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER4_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_4 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER4_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_4 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER4_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_4 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER4_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_4 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER4_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_4 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER4_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_4 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_5 | FCLK | MAIN_TIMER_CLKSEL.OUT5 | 1 | TIMER5_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_5 | FCLK | MAIN_TIMER_4.TIMER_PWM | 1 | TIMER5_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_5 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_6 | FCLK | HFOSC_0 | 1 | TIMER6_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_6 | FCLK | HFOSC_1 | 1 | TIMER6_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_6 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER6_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_6 | FCLK | CLK_12M_RC | 1 | TIMER6_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_6 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER6_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_6 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER6_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_6 | FCLK | EXT_REFCLK1 | 1 | TIMER6_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_6 | FCLK | LFOSC | 1 | TIMER6_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_6 | FCLK | CPTS0_RFT_CLK | 1 | TIMER6_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_6 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER6_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_6 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER6_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_6 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER6_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_6 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER6_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_6 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER6_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_6 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER6_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_6 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER6_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_6 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_7 | FCLK | MAIN_TIMER_CLKSEL.OUT7 | 1 | TIMER7_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_7 | FCLK | MAIN_TIMER_6.TIMER_PWM | 1 | TIMER7_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_7 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_8 | FCLK | HFOSC_0 | 1 | TIMER8_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_8 | FCLK | HFOSC_1 | 1 | TIMER8_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_8 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER8_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_8 | FCLK | CLK_12M_RC | 1 | TIMER8_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_8 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER8_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_8 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER8_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_8 | FCLK | EXT_REFCLK1 | 1 | TIMER8_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_8 | FCLK | LFOSC | 1 | TIMER8_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_8 | FCLK | CPTS0_RFT_CLK | 1 | TIMER8_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_8 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER8_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_8 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER8_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_8 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER8_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_8 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER8_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_8 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER8_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_8 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER8_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_8 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER8_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_8 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_9 | FCLK | MAIN_TIMER_CLKSEL.OUT9 | 1 | TIMER9_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_9 | FCLK | MAIN_TIMER_8.TIMER_PWM | 1 | TIMER9_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_9 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_10 | FCLK | HFOSC_0 | 1 | TIMER10_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_10 | FCLK | HFOSC_1 | 1 | TIMER10_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_10 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER10_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_10 | FCLK | CLK_12M_RC | 1 | TIMER10_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_10 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER10_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_10 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER10_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_10 | FCLK | EXT_REFCLK1 | 1 | TIMER10_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_10 | FCLK | LFOSC | 1 | TIMER10_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_10 | FCLK | CPTS0_RFT_CLK | 1 | TIMER10_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_10 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER10_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_10 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER10_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_10 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER10_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_10 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER10_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_10 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER10_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_10 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER10_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_10 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER10_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_10 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_11 | FCLK | MAIN_TIMER_CLKSEL.OUT11 | 1 | TIMER11_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_11 | FCLK | MAIN_TIMER_10.TIMER_PWM | 1 | TIMER11_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_11 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_12 | FCLK | HFOSC_0 | 1 | TIMER12_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_12 | FCLK | HFOSC_1 | 1 | TIMER12_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_12 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER12_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_12 | FCLK | CLK_12M_RC | 1 | TIMER12_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_12 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER12_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_12 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER12_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_12 | FCLK | EXT_REFCLK1 | 1 | TIMER12_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_12 | FCLK | LFOSC | 1 | TIMER12_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_12 | FCLK | CPTS0_RFT_CLK | 1 | TIMER12_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_12 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER12_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_12 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER12_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_12 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER12_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_12 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER12_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_12 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER12_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_12 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER12_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_12 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER12_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_12 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_13 | FCLK | MAIN_TIMER_CLKSEL.OUT13 | 1 | TIMER13_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_13 | FCLK | MAIN_TIMER_12.TIMER_PWM | 1 | TIMER13_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_13 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_14 | FCLK | HFOSC_0 | 1 | TIMER14_CLKSEL[3:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_TIMER_14 | FCLK | HFOSC_1 | 1 | TIMER14_CLKSEL[3:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_TIMER_14 | FCLK | MAIN_PLL_0.HSDIVOUT8_CLK | 1 | TIMER14_CLKSEL[3:0] | 2 | 0 | |
MAIN_TIMER_14 | FCLK | CLK_12M_RC | 1 | TIMER14_CLKSEL[3:0] | 3 | 0 | 12 MHz |
MAIN_TIMER_14 | FCLK | MAIN_PLL_3.HSDIVOUT3_CLK | 1 | TIMER14_CLKSEL[3:0] | 4 | 0 | |
MAIN_TIMER_14 | FCLK | MCU_EXT_REFCLK0 | 1 | TIMER14_CLKSEL[3:0] | 5 | 0 | |
MAIN_TIMER_14 | FCLK | EXT_REFCLK1 | 1 | TIMER14_CLKSEL[3:0] | 6 | 0 | |
MAIN_TIMER_14 | FCLK | LFOSC | 1 | TIMER14_CLKSEL[3:0] | 7 | 0 | 32 KHz |
MAIN_TIMER_14 | FCLK | CPTS0_RFT_CLK | 1 | TIMER14_CLKSEL[3:0] | 8 | 0 | |
MAIN_TIMER_14 | FCLK | MAIN_PLL_1.HSDIVOUT3_CLK | 1 | TIMER14_CLKSEL[3:0] | 9 | 0 | |
MAIN_TIMER_14 | FCLK | MAIN_PLL_2.HSDIVOUT6_CLK | 1 | TIMER14_CLKSEL[3:0] | 10 | 0 | |
MAIN_TIMER_14 | FCLK | MAIN_PLL_4.HSDIVOUT2_CLK | 1 | TIMER14_CLKSEL[3:0] | 11 | 0 | |
MAIN_TIMER_14 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF2 | 1 | TIMER14_CLKSEL[3:0] | 12 | 0 | |
MAIN_TIMER_14 | FCLK | NAVSS512J7AM_MAIN_0.CPTS0_GENF3 | 1 | TIMER14_CLKSEL[3:0] | 13 | 0 | |
MAIN_TIMER_14 | FCLK | MAIN_CPSW2_0.CPTS_GENF0 | 1 | TIMER14_CLKSEL[3:0] | 14 | 0 | |
MAIN_TIMER_14 | FCLK | MAIN_CPSW9_0.CPTS_GENF0 | 1 | TIMER14_CLKSEL[3:0] | 15 | 0 | |
MAIN_TIMER_14 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_15 | FCLK | MAIN_TIMER_CLKSEL.OUT15 | 1 | TIMER15_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_15 | FCLK | MAIN_TIMER_14.TIMER_PWM | 1 | TIMER15_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_15 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_16 | FCLK | MAIN_TIMER_CLKSEL.OUT16 | 1 | TIMER16_CLKSEL[23:23] | 0 | 0 | |
MAIN_TIMER_16 | FCLK | MAIN_TIMER16_AFS_SEL.OUT0 | 1 | TIMER16_CLKSEL[23:23] | 1 | 0 | |
MAIN_TIMER_16 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_17 | FCLK | MAIN_TIMER17_AFS_EN.OUT0 | 1 | TIMER17_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_17 | FCLK | MAIN_TIMER_16.TIMER_PWM | 1 | TIMER17_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_17 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_18 | FCLK | MAIN_TIMER_CLKSEL.OUT18 | 1 | TIMER18_CLKSEL[23:23] | 0 | 0 | |
MAIN_TIMER_18 | FCLK | MAIN_TIMER18_AFS_SEL.OUT0 | 1 | TIMER18_CLKSEL[23:23] | 1 | 0 | |
MAIN_TIMER_18 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_TIMER_19 | FCLK | MAIN_TIMER19_AFS_EN.OUT0 | 1 | TIMER19_CTRL[8:8] | 0 | 0 | |
MAIN_TIMER_19 | FCLK | MAIN_TIMER_18.TIMER_PWM | 1 | TIMER19_CTRL[8:8] | 1 | 0 | |
MAIN_TIMER_19 | TIMER_ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_0 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_0 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_1 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_1 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_2 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_2 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_3 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_3 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_4 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_4 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_5 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_5 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_6 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_6 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_7 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_7 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_8 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_8 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_9 | FCLK | MAIN_PLL_1.HSDIVOUT0_CLK | 1 | ||||
MAIN_UART_9 | VBUS_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UART_10 | FCLK | MCU_PLL_1.HSDIVOUT3_CLK | 1 | MCU_USART_CLKSEL[0:0] | 0 | 0 | |
MAIN_UART_10 | FCLK | MAIN_PLL_1.HSDIVOUT5_CLK | 1 | MCU_USART_CLKSEL[0:0] | 1 | 0 | |
MAIN_UART_10 | VBUS_CLK | MCU_SYSCLK0 | 6 | 167 MHz | |||
MAIN_UFS_0 | UFSHCI_HCLK_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_UFS_0 | UFSHCI_MCLK_CLK | HFOSC_0 | 1 | UFS0_CLKSEL[1:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_UFS_0 | UFSHCI_MCLK_CLK | HFOSC_1 | 1 | UFS0_CLKSEL[1:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_UFS_0 | UFSHCI_MCLK_CLK | MAIN_PLL_1.HSDIVOUT6_CLK | 1 | UFS0_CLKSEL[1:0] | 2 | 0 | |
MAIN_UFS_0 | UFSHCI_MCLK_CLK | EXT_REFCLK1 | 1 | UFS0_CLKSEL[1:0] | 3 | 0 | |
MAIN_USB_0 | ACLK_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_USB_0 | BUFCLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_USB_0 | CLK_LPM | MAIN_PLL_1.HSDIVOUT7_CLK | 1 | ||||
MAIN_USB_0 | PCLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_USB_0 | PIPE_REFCLK | MAIN_SERDES_0.IP3_LN3_REFCLK | 1 | USB0_CTRL[27:27] | 0 | 0 | |
MAIN_USB_0 | PIPE_REFCLK | MAIN_SERDES_4.IP3_LN3_REFCLK | 1 | USB0_CTRL[27:27] | 1 | 0 | |
MAIN_USB_0 | PIPE_RXCLK | MAIN_SERDES_0.IP3_LN3_RXCLK | 1 | USB0_CTRL[27:27] | 0 | 0 | |
MAIN_USB_0 | PIPE_RXCLK | MAIN_SERDES_4.IP3_LN3_RXCLK | 1 | USB0_CTRL[27:27] | 1 | 0 | |
MAIN_USB_0 | PIPE_RXFCLK | MAIN_SERDES_0.IP3_LN3_RXFCLK | 1 | USB0_CTRL[27:27] | 0 | 0 | |
MAIN_USB_0 | PIPE_RXFCLK | MAIN_SERDES_4.IP3_LN3_RXFCLK | 1 | USB0_CTRL[27:27] | 1 | 0 | |
MAIN_USB_0 | PIPE_TXFCLK | MAIN_SERDES_0.IP3_LN3_TXFCLK | 1 | USB0_CTRL[27:27] | 0 | 0 | |
MAIN_USB_0 | PIPE_TXFCLK | MAIN_SERDES_4.IP3_LN3_TXFCLK | 1 | USB0_CTRL[27:27] | 1 | 0 | |
MAIN_USB_0 | PIPE_TXMCLK | MAIN_SERDES_0.IP3_LN3_TXMCLK | 1 | USB0_CTRL[27:27] | 0 | 0 | |
MAIN_USB_0 | PIPE_TXMCLK | MAIN_SERDES_4.IP3_LN3_TXMCLK | 1 | USB0_CTRL[27:27] | 1 | 0 | |
MAIN_USB_0 | USB2_APB_PCLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_USB_0 | USB2_REFCLOCK | HFOSC_0 | 1 | USB0_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_USB_0 | USB2_REFCLOCK | HFOSC_1 | 1 | USB0_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_VPAC_0 | LDC0_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_0 | LDC0_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_0 | MAIN_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_0 | MAIN_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_0 | MSC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_0 | MSC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_0 | NF_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_0 | NF_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_0 | PSIL_LEAF_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_VPAC_0 | VISS0_CLK_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_0 | VISS0_CLK_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_1 | LDC0_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_1 | LDC0_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_1 | MAIN_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_1 | MAIN_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_1 | MSC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_1 | MSC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_1 | NF_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_1 | NF_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_1 | PSIL_LEAF_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_VPAC_1 | VISS0_CLK_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_1 | VISS0_CLK_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_RTI_GPU | FCLK | HFOSC_0 | 1 | WWD15_CLKSEL[2:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_RTI_GPU | FCLK | LFOSC | 1 | WWD15_CLKSEL[2:0] | 1 | 0 | 32 KHz |
MAIN_RTI_GPU | FCLK | CLK_12M_RC | 1 | WWD15_CLKSEL[2:0] | 2 | 0 | 12 MHz |
MAIN_RTI_GPU | FCLK | CLK_32K | 1 | WWD15_CLKSEL[2:0] | 3 | 0 | 32 KHz |
MAIN_RTI_GPU | FCLK | HFOSC_1 | 1 | WWD15_CLKSEL[2:0] | 4 | 0 | [19.2, - 27] MHz |
MAIN_RTI_GPU | FCLK | HFOSC_1 | 1 | WWD15_CLKSEL[2:0] | 5 | 0 | [19.2, - 27] MHz |
MAIN_RTI_GPU | FCLK | HFOSC_1 | 1 | WWD15_CLKSEL[2:0] | 6 | 0 | [19.2, - 27] MHz |
MAIN_RTI_GPU | FCLK | HFOSC_1 | 1 | WWD15_CLKSEL[2:0] | 7 | 0 | [19.2, - 27] MHz |
MAIN_RTI_GPU | ICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_1KBYTE_SCRATCHPADRAM_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_2KBYTE_SCRATCHPADRAM_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_512KBYTE_SRAM_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_512KBYTE_SRAM_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_512KBYTE_SRAM_ECC_AGGR_2 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_CSI_RX_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_RX_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_RX_ECC_AGGR_2 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_TX_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_TX_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_TX_ECC_AGGR_BYTE_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CSI_TX_ECC_AGGR_BYTE_1 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_DDR_CFG_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CFG_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CFG_ECC_AGGR_2 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CFG_ECC_AGGR_3 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CTL_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CTL_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CTL_ECC_AGGR_2 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_CTL_ECC_AGGR_3 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_VBUS_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_VBUS_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_VBUS_ECC_AGGR_2 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DDR_VBUS_ECC_AGGR_3 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_DSS_DSI_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 1 | [] | 0 | -1 | 500 MHz |
MAIN_DSS_DSI_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 1 | [] | 0 | -1 | 500 MHz |
MAIN_DSS_DSI_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | [] | 1 | -1 | |
MAIN_DSS_DSI_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | [] | 1 | -1 | |
MAIN_DSS_EDP_CORE_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 1 | [] | 0 | -1 | 500 MHz |
MAIN_DSS_EDP_CORE_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | [] | 1 | -1 | |
MAIN_DSS_EDP_DSC_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 1 | [] | 0 | -1 | 500 MHz |
MAIN_DSS_EDP_DSC_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | [] | 1 | -1 | |
MAIN_DSS_EDP_PHY_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 1 | [] | 0 | -1 | 500 MHz |
MAIN_DSS_EDP_PHY_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT7_CLK | 1 | [] | 1 | -1 | |
MAIN_EFUSE_0 | PLL_CTRL_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_EFUSE_0 | WKUP_OSC0_CLK | HFOSC_0 | 1 | EFUSE_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_EFUSE_0 | WKUP_OSC0_CLK | MAIN_SYSCLK0 | 1 | EFUSE_CLKSEL[0:0] | 1 | 0 | 500 MHz |
MAIN_EMMC4_RX_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_EMMC4_TX_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_EMMC8_RX_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_EMMC8_TX_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_INTROUTER_GPIOMUX_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_1 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_10 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_11 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_12 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_13 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_14 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_15 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_16 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_17 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_2 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_3 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_4 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_5 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_6 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_7 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_8 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MCANSS_ECC_AGGR_9 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MMR_CTRL_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MMR_PLL_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_MMR_SEC_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PLL_0 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL0_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_0 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL0_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_0 | POSTDIV_CLKIN_CLK | MAIN_PLL_0.FOUTPOSTDIV_CLK | 1 | ||||
MAIN_PLL_0 | VCO_CLKIN_CLK | MAIN_PLL_0.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_1 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL1_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_1 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL1_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_1 | POSTDIV_CLKIN_CLK | MAIN_PLL_1.FOUTPOSTDIV_CLK | 1 | ||||
MAIN_PLL_1 | VCO_CLKIN_CLK | MAIN_PLL_1.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_2 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL2_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_2 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL2_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_2 | POSTDIV_CLKIN_CLK | MAIN_PLL_2.FOUTPOSTDIV_CLK | 1 | ||||
MAIN_PLL_2 | VCO_CLKIN_CLK | MAIN_PLL_2.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_3 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL3_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_3 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL3_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_3 | VCO_CLKIN_CLK | MAIN_PLL_3.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_4 | FREF_CLK | MAIN_PLL_HFOSC_SEL.OUT4 | 1 | MAIN_PLL4_CLKSEL[4:4] | 0 | 0 | |
MAIN_PLL_4 | FREF_CLK | EXT_REFCLK1 | 1 | MAIN_PLL4_CLKSEL[4:4] | 1 | 0 | |
MAIN_PLL_4 | VCO_CLKIN_CLK | MAIN_PLL_4.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_5 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL5_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_5 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL5_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_5 | VCO_CLKIN_CLK | MAIN_PLL_5.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_6 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL6_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_6 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL6_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_6 | VCO_CLKIN_CLK | MAIN_PLL_6.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_7 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL7_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_7 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL7_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_7 | VCO_CLKIN_CLK | MAIN_PLL_7.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_8 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL8_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_8 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL8_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_8 | VCO_CLKIN_CLK | MAIN_PLL_8.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_9 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL9_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_9 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL9_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_9 | VCO_CLKIN_CLK | MAIN_PLL_9.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_12 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL12_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_12 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL12_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_12 | VCO_CLKIN_CLK | MAIN_PLL_12.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_14 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL14_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_14 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL14_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_14 | VCO_CLKIN_CLK | MAIN_PLL_14.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_16 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL16_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_16 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL16_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_16 | VCO_CLKIN_CLK | MAIN_PLL_16.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_17 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL17_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_17 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL17_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_17 | VCO_CLKIN_CLK | MAIN_PLL_17.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_19 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL19_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_19 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL19_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_19 | VCO_CLKIN_CLK | MAIN_PLL_19.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_25 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL25_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_25 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL25_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_25 | VCO_CLKIN_CLK | MAIN_PLL_25.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_26 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL26_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_26 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL26_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_26 | VCO_CLKIN_CLK | MAIN_PLL_26.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_27 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL27_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_27 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL27_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_27 | VCO_CLKIN_CLK | MAIN_PLL_27.FOUTVCOP_CLK | 1 | ||||
MAIN_PLL_28 | FREF_CLK | HFOSC_0 | 1 | MAIN_PLL28_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLL_28 | FREF_CLK | HFOSC_1 | 1 | MAIN_PLL28_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLL_28 | VCO_CLKIN_CLK | MAIN_PLL_28.FOUTVCOP_CLK | 1 | ||||
MAIN_PLLCTRL_0 | PLL_CLKOUT_CLK | MAIN_PLL_0.HSDIVOUT0_CLK | 1 | ||||
MAIN_PLLCTRL_0 | PLL_REFCLK_CLK | HFOSC_0 | 1 | MAIN_PLL0_CLKSEL[0:0] | 0 | 0 | [19.2, 20, 24, 25, 26, 27] MHz |
MAIN_PLLCTRL_0 | PLL_REFCLK_CLK | HFOSC_1 | 1 | MAIN_PLL0_CLKSEL[0:0] | 1 | 0 | [19.2, - 27] MHz |
MAIN_PLLCTRL_0 | VBUS_SLV_REFCLK_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_SA2_UL_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_UFS_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_USB3_ECC_AGGR_0 | ECC_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_VPAC_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_LDC_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_LDC_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_LDC_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_LDC_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_VISS_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_VISS_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_25.HSDIVOUT1_CLK | 1 | 0 | |||
MAIN_VPAC_VISS_ECC_AGGR_0 | ECC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
MAIN_VPAC_VISS_ECC_AGGR_1 | ECC_CLK | MAIN_PLL_2.HSDIVOUT1_CLK | 1 | 1 | |||
DEBUGSS_0 | ATB_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
DEBUGSS_0 | CORE_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
DEBUGSS_0 | JTAG_TCK | TCK | 1 | ||||
DEBUGSS_0 | TREXPT_CLK | MAIN_PLL_2.HSDIVOUT3_CLK | 1 | ||||
MAIN_CPT2_AC_AGGR_0 | CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_ACP_AGGR_0 | CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_HC_AGGR_0 | CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_MI_AGGR_0 | CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_MV_AGGR_0 | CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_DMPAC_SRAM_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_DMPAC_SRAM_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_DDR_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_DDR_RESP_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_DDR_RESP_2 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_DDR_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_DDR_RESP_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_DDR_RESP_2 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_SRAM_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_NAV_SRAM_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_AC_VPAC_SRAM_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_VPAC_SRAM_RESP_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_AC_VPAC_SRAM_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_AC_VPAC_SRAM_RESP_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_ACP_SRAM_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_ACP_SRAM_RESP_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_ACP_SRAM_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_ACP_SRAM_RESP_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_HC_HYPERLINK_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_HC_HYPERLINK_RESP_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_HC_HYPERLINK_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_HC_HYPERLINK_RESP_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_HC_PCIE_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_HC_PCIE_RESP_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_HC_PCIE_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_HC_PCIE_RESP_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_MI_SRAM_RESP_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_MI_SRAM_RESP_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_DDR_INIT_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_DDR_INIT_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_DDR_INIT_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_DDR_INIT_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_HMST_INIT_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_HMST_INIT_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_LMST_INIT_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_LMST_INIT_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_SRAM_INIT_0 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_SRAM_INIT_1 | AGGR_CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_SRAM_INIT_0 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_PROBE_RC_NAV_SRAM_INIT_1 | PROBE_CLK | MAIN_SYSCLK0 | 1 | 500 MHz | |||
MAIN_CPT2_RC_AGGR_0 | CLK | MAIN_SYSCLK0 | 2 | 250 MHz | |||
MAIN_ELM_0 | FICLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_AC_EDP_DSI_0 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_HC_0 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_INFRA_0 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_INFRA_1 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_NAVSS_0 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_R5FSS_0 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_R5FSS_1 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz | |||
MAIN_PBIST_R5FSS_2 | CLK8_CLK | MAIN_SYSCLK0 | 4 | 125 MHz |