SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
The inter-processor communication registers in the CTRL_MMR modules are used for generating interrupts to the device cores. Any master having access to these registers can generate an interrupt by writing 1h to the IPC_SETx[0] bits. The interrupt is cleared when 1h is written to the IPC_CLRx[0] bits. These registers provide also a Source ID facility through the IPC_SETx[31-4] IPC_SRC_SET and IPC_CLRx[31-4] IPC_SRC_CLR bit fields by which up to 28 different sources of interrupts can be identified. Allocation of the source bits to source processor and meaning is entirely based on software convention. Virtually, anything can be a source for these fields as this is completely controlled by software.
Writing 1h to an IPC_SRC_SET bit sets to 1h both the IPC_SRC_SET and corresponding IPC_SRC_CLR bit. Writing 1h to an IPC_SRC_CLR bit sets to 0h (clears) both the IPC_SRC_CLR and corresponding IPC_SRC_SET bit. The same logic applies also to the IPC_SETx[0] IPC_SET and IPC_CLRx[0] IPC_CLR bits. Table 5-5 and Table 5-6 shows the mapping between the inter-processor communication (IPC) registers and device cores.
IPC Register Instance "x"1 CTRL_MMR0_IPC_SETx CTRL_MMR0_IPC_CLRx |
Device Core |
---|---|
0 | C7SS0 |
1 | C7SS1 |
8 | A72SS0 core 0 |
9 | A72SS0 core 1 |
16 | R5FSS0 core 0 |
17 | R5FSS0 core 1 |
18 | R5FSS1 core 0 |
19 | R5FSS1 core 1 |
IPC Register Instance "x"1 MCU_CTRL_MMR0_IPC_SETx MCU_CTRL_MMR0_IPC_CLRx |
Device Core |
---|---|
0 | MCU R5 core0 |
1 | MCU R5 core1 |
8 | DMSC |
For latency reasons the IPC registers are not write protected by KICK registers which means that they can be written to without a need for performing unlocking procedure as described in Section 5.1.2.3.