SPRUJ52C june 2022 – july 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
Many CPUs can be restarted (from a debug halt state) by asserting a signal on their module boundary. The EXECUTEACTION directive is associated to this signal. When the associated CPU is configured for this type of execution (this is a core specific function), setting this directive will cause the CPU to resume execution. Since this resume function can be accomplished without an active debug connection to the CPU, the managed domain can immediately move to its natural power state without impacting debug.
The GLOBALEXEMASK system directive can be used to mask multiple EXECUTEACTION subdomain directives. This mask can be removed with a single tools write, which will assert the "restart" signal to a set of CPUs simultaneously, thus providing pseudo-synchronous restart capabilities across multiple CPUs in multiple managed domains.
The debug tools can also request that CPU(s) in the managed domain halt immediately after reset. The RESETCONTROL directive supports modes for halt-on-reset. When in these modes, a debug halt request to the CPU(s) in the managed domain is asserted and maintained whenever a functional reset request is detected. This results in a CPU halt as soon as the reset is released and the CPU enters a state where debug halts are excepted. This halts the CPU at the first "debugable" instruction in the boot sequence.