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SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1

14.8.6.3.2.17 DPHY_TX_WIZ_CONFIG_IPCONFIG Register

3.2.17.1 DPHY_TX_WIZ_CONFIG_IPCONFIG Register (Offset = 14h) [reset = 1h]

IP Config

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Table 14-23345 Instance Table

Instance Name	Physical Address
DPHY_TX0	301C 0014h

Figure 14-11558 DPHY_TX_WIZ_CONFIG_IPCONFIG Name Register

31	30	29	28	27	26	25	24
PSO_CMN	RESERVED
R/W	NONE
0h	0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED					IPCONFIG_CMN
NONE					R/W
0h					1h

Table 14-23346 DPHY_TX_WIZ_CONFIG_IPCONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PSO_CMN	R/W	0h	Power Shutoff signal for CMN 1: CMN is power OFF 0: CMN is power ON
30:3	RESERVED	NONE	0h	Reserved
2:0	IPCONFIG_CMN	R/W	1h	This signal decides which clock lane acts as initiator clock lane to all data lanes. Needed only for RXIP. Bit[2]: Reserved CASE {Bit[1],Bit[0]}: 00: Left RX clk lane provides clock to all left and right data lanes. 01: Left RX clk lane provides clock to all right data lanes, Right RX clk lane provides clock to all left data lanes. 10: Right RX clk lane provides clock to all right data lanes, Left RX clk lane provides clock to all left data lanes. 11: Right RX clk lane provides clock to all left and right data lanes.