SPRUJ83 User guide | 德州仪器 TI.com.cn

SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1

14.8.6.3.2.9 DPHY_TX_DPHYTX_DL3_TX_DIG_TBIT20 Register

3.2.9.1 DPHY_TX_DPHYTX_DL3_TX_DIG_TBIT20 Register (Offset = 56Ch) [reset = 0h]

digital to analog signal muxing

Table 14-23329 Instance Table

Instance Name	Physical Address
DPHY_TX0	301C 056Ch

Figure 14-11550 DPHY_TX_DPHYTX_DL3_TX_DIG_TBIT20 Name Register

31	30	29	28	27	26	25	24
DL3_TM_ISO_EN	DL3_TM_LOAD_DPDN_SEL	DL3_TM_LOAD_DPDN			DL3_TM_HSTX_DATA_RATE_SEL	DL3_TM_HSTX_DATE_RATE
R/W	R/W	R/W			R/W	R/W
0h	0h	0h			0h	0h
23	22	21	20	19	18	17	16
DL3_TM_BIST_ULP_RCV_EN_SEL	DL3_TM_BIST_ULP_RCV_EN	DL3_TM_ULPS_PULDN_SEL	DL3_TM_ULPS_PULDN	DL3_TM_BIST_SMPLR_CLK_EDGE_SEL	DL3_TM_BIST_SMPLR_CLK_EDGE	DL3_TM_BIST_EN_SEL	DL3_TM_BIST_EN
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
DL3_TM_LPTX_TRST_SEL	DL3_TM_LPTX_TRST	DL3_TM_LPTX_RST_SEL	DL3_TM_LPTX_RST	DL3_TM_LPTX_DP_SEL	DL3_TM_LPTX_DP	DL3_TM_LPTX_DN_SEL	DL3_TM_LPTX_DN
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
DL3_TM_LDO_REF_EN_SEL	DL3_TM_LDO_REF_EN	DL3_TM_HSTX_TRST_SEL	DL3_TM_HSTX_TRST	DL3_TM_HSTX_RQST_SEL	DL3_TM_HSTX_RQST	DL3_TM_GLOBAL_PD_SEL	DL3_TM_GLOBAL_PD
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 14-23330 DPHY_TX_DPHYTX_DL3_TX_DIG_TBIT20 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DL3_TM_ISO_EN	R/W	0h	Enable isolation in test mode
30	DL3_TM_LOAD_DPDN_SEL	R/W	0h	Take ana_dpdn_load from dig logic
29:27	DL3_TM_LOAD_DPDN	R/W	0h	set ana_dpdn_load as per requirement in test mode
26	DL3_TM_HSTX_DATA_RATE_SEL	R/W	0h	Take ana_hstx_datarate from dig logic
25:24	DL3_TM_HSTX_DATE_RATE	R/W	0h	set ana_hstx_datarate as per requirement in test mode
23	DL3_TM_BIST_ULP_RCV_EN_SEL	R/W	0h	Take ana_bist_ulps_rcv_en from dig logic
22	DL3_TM_BIST_ULP_RCV_EN	R/W	0h	set ana_bist_ulps_rcv_en to 0
21	DL3_TM_ULPS_PULDN_SEL	R/W	0h	Take ana_ulps_puldn from dig logic
20	DL3_TM_ULPS_PULDN	R/W	0h	set ana_ulps_puldn to 0
19	DL3_TM_BIST_SMPLR_CLK_EDGE_SEL	R/W	0h	Take ana_bist_smplr_clkedge from dig logic
18	DL3_TM_BIST_SMPLR_CLK_EDGE	R/W	0h	set ana_bist_smplr_clkedge to posedge
17	DL3_TM_BIST_EN_SEL	R/W	0h	Take ana_bist_en from dig logic
16	DL3_TM_BIST_EN	R/W	0h	set ana_bist_en to 0
15	DL3_TM_LPTX_TRST_SEL	R/W	0h	Take ana_lptx_trst from dig logic
14	DL3_TM_LPTX_TRST	R/W	0h	set ana_lptx_trst to 0
13	DL3_TM_LPTX_RST_SEL	R/W	0h	Take ana_lptx_rst from dig logic
12	DL3_TM_LPTX_RST	R/W	0h	set ana_lptx_rst to 0
11	DL3_TM_LPTX_DP_SEL	R/W	0h	give output for LPTX DP from dig logic
10	DL3_TM_LPTX_DP	R/W	0h	send 0 to LP TX Dp
9	DL3_TM_LPTX_DN_SEL	R/W	0h	give output for LPTX DN from dig logic
8	DL3_TM_LPTX_DN	R/W	0h	send 0 to LP TX Dn
7	DL3_TM_LDO_REF_EN_SEL	R/W	0h	Take ana_ldo_ref_en from dig logic
6	DL3_TM_LDO_REF_EN	R/W	0h	set ana_ldo_ref_en to 0
5	DL3_TM_HSTX_TRST_SEL	R/W	0h	Take ana_hstx_trst from dig logic
4	DL3_TM_HSTX_TRST	R/W	0h	set ana_hstx_trst to 0
3	DL3_TM_HSTX_RQST_SEL	R/W	0h	Take ana_hstx_rqst from dig logic
2	DL3_TM_HSTX_RQST	R/W	0h	set ana_hstx_rqst to 0
1	DL3_TM_GLOBAL_PD_SEL	R/W	0h	Take ana_global_pd from dig logic
0	DL3_TM_GLOBAL_PD	R/W	0h	set ana_global_pd to 0 (powered up)