SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8530h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | INHIBIT_DRAM_CMD | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | DISABLE_RD_INTERLEAVE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SWAP_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NUM_Q_ENTRIES_ACT_DISABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | INHIBIT_DRAM_CMD | R/W | 0h | Inhibit command types from being executed from the command queue. Clear to 0 to enable any command, program to 1 to inhibit read/write and bank commands, program to 2 to inhibit MRR and peripheral MRR commands, or program to 3 to inhibit MRR and read/write commands. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | DISABLE_RD_INTERLEAVE | R/W | 0h | Disable read data interleaving for commands from the same port, regardless of the requestor ID. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | SWAP_EN | R/W | 0h | Enable command swapping logic in execution unit. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | NUM_Q_ENTRIES_ACT_DISABLE | R/W | 0h | Number of queue entries in which ACT requests will be disabled. Programming to X will disable ACT requests from the X entries lowest in the command queue. Reset Source: ctl_amod_g_rst_n |