SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A4B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_SLICE_PER_DEV_1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_SLICE_PER_DEV_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_VREF_VAL_DEV3_3 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_VREF_VAL_DEV3_2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PI_SLICE_PER_DEV_1 | R/W | 0h | Indicates the number of data slices per memory device. The device width divided by 8. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_SLICE_PER_DEV_0 | R/W | 0h | Indicates the number of data slices per memory device. The device width divided by 8. Reset Source: ctl_amod_g_rst_n |
| 15 | RESERVED | NONE | 0h | Reserved |
| 14:8 | PI_VREF_VAL_DEV3_3 | R/W | 0h | Defines the range and value for VREF training for DRAM 3 for CS 3. If the PI_VREF_PDA_EN parameter is not set, device 0 values are used for all devices. Reset Source: ctl_amod_g_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6:0 | PI_VREF_VAL_DEV3_2 | R/W | 0h | Defines the range and value for VREF training for DRAM 3 for CS 2. If the PI_VREF_PDA_EN parameter is not set, device 0 values are used for all devices. Reset Source: ctl_amod_g_rst_n |