SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 84A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ZQ_CALSTART_NORM_THRESHOLD_F0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ZQ_CALSTART_NORM_THRESHOLD_F0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ZQCS_OPT_THRESHOLD | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | AREF_CMD_MAX_PER_TREFI | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | ZQ_CALSTART_NORM_THRESHOLD_F0 | R/W | 0h | ZQ START number of long counts until the normal priority request is asserted. This value should be scaled based on the number of ranks [chip selects] the controller handles. The more chip selects there are, the more rotations there are to go through, and the smaller this threshold should be. FC=0 Reset Source: ctl_amod_g_rst_n |
| 15:11 | RESERVED | NONE | 0h | Reserved |
| 10:8 | ZQCS_OPT_THRESHOLD | R/W | 0h | Number of clocks before ZQCS expires when the ZQ task will deassert its request for optimal command to command turn-around timing. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | AREF_CMD_MAX_PER_TREFI | R/W | 0h | Sets the maximum number of auto-refreshes that will be executed in a TREFI period - both normal and high priority. This does not prevent refreshes generated by sub-task requests such as a self-refresh exit and enter. Reset Source: ctl_amod_g_rst_n |