SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 849Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | LONG_COUNT_MASK | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | BIST_RET_STATE_EXIT | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | BIST_ERR_COUNT | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BIST_ERR_COUNT | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | LONG_COUNT_MASK | R/W | 0h | Reduces the length of the long counter from 1024 cycles. The only supported values are 0x00 [1024 cycles], 0x10 [512 clocks], 0x18 [256 clocks], 0x1C [128 clocks], 0x1E [64 clocks] and 0x1F [32 clocks]. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | BIST_RET_STATE_EXIT | W | 0h | Exit self-refresh or idle retention state, used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Set to 1 to trigger. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:0 | BIST_ERR_COUNT | R | 0h | Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is programmed to 1, 2 or 3. READ-ONLY Reset Source: ctl_amod_g_rst_n |