SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A074h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_WRLVL_CS_MAP | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_WRLVL_ROTATE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_WRLVL_RESP_MASK | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_WRLVL_DISABLE_DFS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PI_WRLVL_CS_MAP | R/W | 0h | Defines the chip select map for write leveling operations. Bit [0] controls cs0, bit [1] controls cs1, etc. Set each bit to 1 to enable chip for write leveling. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_WRLVL_ROTATE | R/W | 0h | Enables rotational CS for counter triggered automatic write leveling. Set to 1, only one rank's write levling will process, the rank number is rotational for each time that write leveling been triggered by counter expiring. Set to 0 or not a short pattern leveling [indicated by dfi_lvl_periodic], the counter expired write leveling will process all the ranks. Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PI_WRLVL_RESP_MASK | R/W | 0h | Mask for the dfi_wrlvl_resp signal during write leveling. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_WRLVL_DISABLE_DFS | R/W | 0h | Disable automatic write leveling on freq change. Set to 1 to disable wrlvl on dfs,set 0 enable wrlvl on dfs. Reset Source: ctl_amod_g_rst_n |