SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A0A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PI_RDLVL_PAT_2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PI_RDLVL_PAT_2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PI_RDLVL_PAT_2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_RDLVL_PAT_2 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | PI_RDLVL_PAT_2 | R/W | 0h | Non-default pattern 2 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4. Reset Source: ctl_amod_g_rst_n |