SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8624h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | TDQSCK_MAX_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | W2W_SAMECS_DLY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | W2R_SAMECS_DLY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | R2R_SAMECS_DLY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | TDQSCK_MAX_F0 | R/W | 0h | Additional delay needed for tDQSCK. FC=0 Reset Source: ctl_amod_g_rst_n |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20:16 | W2W_SAMECS_DLY | R/W | 0h | Additional delay to insert between two writes to the same chip select. Any value including 0 supported. Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | W2R_SAMECS_DLY | R/W | 0h | Additional delay to insert between writes and reads to the same chip select. Reset Source: ctl_amod_g_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | R2R_SAMECS_DLY | R/W | 0h | Additional delay to insert between two reads to the same chip select. Any value including 0 supported. Reset Source: ctl_amod_g_rst_n |