SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DM_DLY_STEP_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DQ_SLV_DELTA_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_PERIODIC_OBS_SELECT_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 | W | 0h | Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 0. Set to 1 to trigger. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 23:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | PHY_WDQLVL_DM_DLY_STEP_0 | R/W | 0h | The target delay line step for DM training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:8 | PHY_WDQLVL_DQ_SLV_DELTA_0 | R/W | 0h | The margin for DQ0-7's LE and TE dealy to make sure the DQ bits can work during DM training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PHY_WDQLVL_PERIODIC_OBS_SELECT_0 | R/W | 0h | Select value to map specific information during or post periodic write data leveling for slice 0. Reset Source: ctl_amod_g_rst_n |